LW rt, offset(rs) |
nanoMIPS, availability varies by format. |
Load Word |
Load Word. Load word to register $rt from memory address $rs + offset (register plusimmediate).
nanoMIPS, availability varies by format.
|
100001 |
rt |
rs |
1000 |
u |
|
6 |
5 |
5 |
4 |
12 |
offset = u
|
000101 |
rt3 |
rs3 |
u[5:2] |
|
6 |
3 |
3 |
4 |
rt = decode_gpr(rt3, 'gpr3') rs = decode_gpr(rs3, 'gpr3') offset = u
|
011101 |
rt4[3] |
u[2] |
rt4[2:0] |
rs4[3] |
u[3] |
rs4[2:0] |
|
6 |
1 |
1 |
3 |
1 |
1 |
3 |
if C0.Config5.NMS == 1:
raise exception('RI')
rt = decode_gpr(rt4[3] @ rt4[2:0], 'gpr4')
rs = decode_gpr(rs4[3] @ rs4[2:0], 'gpr4')
offset = u
|
010101 |
rt3 |
u[8:2] |
|
6 |
3 |
7 |
rt = decode_gpr(rt3, 'gpr3') rs = 28 offset = u
|
010000 |
rt |
u[20:2] |
10 |
|
6 |
5 |
19 |
2 |
rs = 28 offset = u
|
101001 |
rt |
rs |
s[8] |
1000 |
0 |
00 |
s[7:0] |
|
6 |
5 |
5 |
1 |
4 |
1 |
2 |
8 |
offset = sign_extend(s, from_nbits=9)
|
001101 |
rt |
u[6:2] |
|
6 |
5 |
5 |
rs = 29 offset = u
va = effective_address(GPR[rs], offset, 'Load') data = read_memory_at_va(va, nbytes=4) GPR[rt] = sign_extend(data, from_nbits=32)
Address Error. Bus Error. Reserved Instruction for LW[4X4] format on NMS cores. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.