Assembly:

RDHWR rt, hs, sel

Purpose:

Read Hardware Register. Read specific CP0 privileged state (identified by hs, sel) to register$rs. Kernel code can enable or disable user mode RDHWR accesses by programming the enable bits in the HWREna register.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
if not IsCoprocessor0Enabled():
   if not C0.HWREna & (1 << hs):
       raise exception('RI', 'Required HWREnabitnotset')
if sel and hs != 4:
    raise exception('RI', 'sel fieldnot supported for this hs')
if is_guest_mode():
    check_gpsi('CP0')
if hs == 0:
    GPR[rt] = C0.EBase.CPUNum
elif hs == 1:
    GPR[rt] = synci_step()
elif hs == 2:
    if is_guest_mode():
        check_gpsi('GT')
        GPR[rt] = guest_count()
    else:
        GPR[rt] = C0.Count
elif hs == 3:
    GPR[rt] = CPU.count_resolution
elif hs == 4:
    if not C0.Config1.PC:
        raise exception('RI', 'Perf Counters not implemented')
    GPR[rt] = read_cp0_register(25, sel)  # Performance counter register
elif hs == 5:
    GPR[rt] = C0.Config5.XNP
elif hs == 29:
    if not C0.Config3.ULRI:
        raise exception('RI')
    GPR[rt] = sign_extend(C0.UserLocal)
else:
    raise exception('RI')

Exceptions:

Coprocessor Unusable. Reserved Instruction for unsupported register numbers. Reserved Instruction on NMS cores.