Assembly:

UALWM rt, offset(rs), count

Purpose:

Unaligned Load Word Multiple.

Load count words of data to registers $rt, $(rt+1),...,

$(rt+count-1) from consecutive memory address starting at $rs + offset (register plus immediate). Guarantee that the operation completes even if the address is not word aligned.

Availability:

nanoMIPS, not available in NMS

Format:

offset = sign_extend(s, from_nbits=9)
count = 8 if count3 == 0 else count3

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
i = 0
while i != count:
    this_rt = ( rt + i      if rt + i < 32 else
                rt + i - 16                    )
    this_offset = offset + (i<<2)
    va = effective_address(GPR[rs], this_offset, 'Load')
    data = read_memory_at_va(va, nbytes=4, unaligned_support='always')
    GPR[this_rt] = sign_extend(data, from_nbits=32)
    if this_rt == rs and i != count - 1:
        raise UNPREDICTABLE()
    i += 1

UALWM loads count words to sequentially numbered registers from sequential memory addresses which are potentially unaligned. After loading $31, the sequence of registers continues from $16. See

LWM for example encodings of the register list.

UALWM will not cause an Address Error exception for unaligned addresses.

The result is unpredictable if an UALWM instruction updates the base register prior to the final load.

If a TLB exception or interrupt occurs during the execution of this instruction, a subset of the required register updates may have occurred.

An unaligned load/store instruction may be implemented using more than one memory transaction.It is possible for a subset of these memory transactions to have completed and then for a TLB exception to

occur on a remaining transaction.It is also possible that memory could be modified by another thread or device in between the completion of the memory transactions. This behavior is equivalent to what

might occur if the unaligned load/store was carried out in software using a series of separate aligned instructions, for instance using LWL/LWR on a pre-R6 MIPS™ core. Software should take equivalent

steps to accommodate this lack of guaranteed atomicity as it would for the multiple instruction case.

UALWM must be implemented in such a way as to make the instruction restartable, but the implementation does not need to be fully atomic. For instance,

it is allowable for a UALWM instruction to be

aborted by an exception after a subset of the register updates have occurred. To ensure restartability, any write to GPR $rs (which may be used as the final output register) must be completed atomically,

that is, the instruction must graduate if and only if that write occurs.

Exceptions:

Bus Error. Reserved Instruction on NMS cores. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.