Assembly:

SHX rd, rs(rt)

Purpose:

Store Half indeXed. Store halfword from register $rt to memory address $rt + $rs (registerplus register).

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
va = effective_address(GPR[rs], GPR[rt], 'Store')
data = zero_extend(GPR[rd], from_nbits=16)
write_memory_at_va(data, va, nbytes=2)

Exceptions:

Address Error. Bus Error. Reserved Instruction on NMS Cores. TLB Invalid. TLB Modified. TLB Refill. Watch.