SH rt, offset(rs) |
nanoMIPS |
Store Half |
Store Half. Store halfword from register $rt to memory address $rs + offset (register plusimmediate).
nanoMIPS
|
100001 |
rt |
rs |
0101 |
u |
|
6 |
5 |
5 |
4 |
12 |
offset = u
|
011111 |
rtz3 |
rs3 |
0 |
u[2:1] |
1 |
|
6 |
3 |
3 |
1 |
2 |
1 |
rt = decode_gpr(rtz3, 'gpr3.src.store') rs = decode_gpr(rs3, 'gpr3') offset = u
|
010001 |
rt |
101 |
u[17:1] |
0 |
|
6 |
5 |
3 |
17 |
1 |
rs = 28 offset = u
|
101001 |
rt |
rs |
s[8] |
0101 |
0 |
00 |
s[7:0] |
|
6 |
5 |
5 |
1 |
4 |
1 |
2 |
8 |
offset = sign_extend(s, from_nbits=9)
va = effective_address(GPR[rs], offset, 'Store') data = zero_extend(GPR[rt], from_nbits=16) write_memory_at_va(data, va, nbytes=2)
Address Error. Bus Error. TLB Invalid. TLB Modified. TLB Refill. Watch.