Encoding:

P32A

001000

rt

rs

sa

0

100

001

111

111

6

5

5

3

1

3

3

3

3

Format: 

SHLL.QB rt, rs, sa

DSP

Shift Left Logical Vector Quad Bytes

Purpose:

Shift Left Logical Vector Quad Bytes

Element-wise left shift of four independent bytes in a vector data type by a fixed number of bits.

Description: 

rt = (rs31..24 << sa) || (rs23..16 << sa) || (rs15..8 << sa) || (rs7..0 << sa)

The four byte values in register rs are each independently shifted left by sa bits and the sa least significant bits of each value are set to zero. The four independent results are then written to the corresponding byte elements of destination register rt.

This instruction writes a 1 to bi t 22 in the DSPControl register in the ouflag field if any of the left shift operations results in an overflow.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

ValidateAccessToDSPResources()
tempD7..0 = shift8Left( GPR[rs]31..24, sa2..0 )
tempC7..0 = shift8Left( GPR[rs]23..16, sa2..0 )
tempB7..0 = shift8Left( GPR[rs]15..8, sa2..0 )
tempA7..0 = shift8Left( GPR[rs]7..0, sa2..0 )
GPR[rt]31..0 = tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function shift8Left( a7..0, s2..0 )
   if ( s2..0 = 0 ) then
      temp7..0 = a7..0
   else
      sign = a7
      temp7..0 = ( a7-s..0 || 0s )
      discard7..0 = ( sign(8-s) || a6..6-(s-1) )
      if ( discard7..0 != 0x00 ) then
          DSPControlouflag:22 = 1
      endif
   endif
   return temp7..0
endfunction shift8Left

Exceptions:

Reserved Instruction, DSP Disabled