Encoding:

Format:

DPSQ_S.W.PH ac, rs, rt 

Purpose:

Dot Product with Subtraction on Fractional Halfword Elements

Element-wise multiplication of two vectors of fractional halfword elements and subtraction of the accumulated 32-bit intermediate products from the specified 64-bit accumulator register, with saturation.

Description:

ac = ac - (sat32(rs31..16 * rt31..16) + sat32(rs15..0 * rt15..0))

Each of the two Q15 fractional word values from registers rt and rs are multiplied together, and the results left-shifted by one bit position to generate two Q31 fractional format intermediate products. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).

The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is subtracted from the specified 64-bit HI/LO accumulator to produce a f inal Q32.31 fractional result.

The value of ac can range from 0 to 3; a v alue of 0 refers to the original HI/LO register pair of the MIPS32 architecture.

If saturation occurs as a result of a half word multiplication, a 1 is wr itten to one o f bits 16 through 19 of the

DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds

to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ValidateAccessToDSPResources()
tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]31..16 )
tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]15..0 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0
( HI[ac]31..0 || LO[ac]31..0 )  = tempC63..32 || tempC31..0

Exceptions:

Reserved Instruction, DSP Disabled