Encoding:

Format:

CMP.cond.PH 

CMP.EQ.PH  rs, rt

CMP.LT.PH  rs, rt

CMP.LE.PH  rs, rt

Purpose:

Compare Vectors of Signed Integer Halfword Values

Perform an element-wise comparison oftwo vectors of two signed integer halfwords, recording the results of the comparison in condition code bits.

Description:

DSPControlccond:25..24 = (rs31..16 cond rt31..16) || (rs15..0 cond rt15..0)

The two signed integer halfword elements in register rs are compared with the corresponding signed integer halfword element in register rt. The two 1-bit boolean comparison results are written to bits 24 and 25 of the DSPControl register’s 4-bit condition code field. The v alues of t he two remaining condition code bi ts (bits 26 t hrough 27 of the

DSPControl register) are UNPREDICTABLE.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

CMP.EQ.PH
   ValidateAccessToDSPResources()
   ccB = GPR[rs]31..16 EQ GPR[rt]31..16 
   ccA = GPR[rs]15..0 EQ GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:27..26 = UNPREDICTABLE
CMP.LT.PH
   ValidateAccessToDSPResources()
   ccB = GPR[rs]31..16 LT GPR[rt]31..16 
   ccA = GPR[rs]15..0 LT GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:27..26 = UNPREDICTABLE
CMP.LE.PH
   ValidateAccessToDSPResources()
   ccB = GPR[rs]31..16 LE GPR[rt]31..16 
   ccA = GPR[rs]15..0 LE GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA

Exceptions:

Reserved Instruction, DSP Disabled