Assembly:

UASWM rt, offset(rs), count

Purpose:

Unaligned Store Word Multiple. Store count words of data from registers $rt, $(rt+1),

...,

$(rt+count-1) to consecutive memory addresses starting at $rs + offset (register plus immediate). Guarantee that the operation completes even if the address is not word aligned.

Availability:

nanoMIPS, not available in NMS

Format:

offset = sign_extend(s, from_nbits=9)
count = 8 if count3 == 0 else count3

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
i = 0
while i != count:
    this_rt = ( 0           if rt == 0    else
                rt + i      if rt + i < 32 else
                rt + i - 16                    )
    this_offset = offset + (i<<2)
    va = effective_address(GPR[rs], this_offset, 'Store')
    data = zero_extend(GPR[this_rt], from_nbits=32)
    write_memory_at_va(data, va, nbytes=4, unaligned_support='always')
    i += 1

UASWM stores count words from sequentially numbered registers to sequential memory addresses which are potentially unaligned. After storing $31, the sequence of registers continues from $16.If

rt=0, then $0 is stored for all count steps of the instruction. See SWM for example encodings of the register list.

UASWM will not cause an Address Error exception for unaligned addresses.

If a TLB exception or interrupt occurs during the execution of this instruction, a subset of the required memory updates may have occurred. A full restart of the instruction will be performed on return from

the exception.

An unaligned load/store instruction may be implemented using more than one memory transaction.It is possible for a subset of these memory transactions to have completed and then for a TLB exception to

occur on a remaining transaction.It is also possible that memory could be modified by another thread or device in between the completion of the memory transactions. This behavior is equivalent to what

might occur if the unaligned load/store was carried out in software using a series of separate aligned instructions, for instance using LWL/LWR on a pre-R6 MIPS™ core. Software should take equivalent

steps to accommodate this lack of guaranteed atomicity as it would for the multiple instruction case.

Exceptions:

Bus Error. Reserved Instruction on NMS cores. TLB Invalid. TLB Modified. TLB Refill. Watch.