Encoding:

P32A

001000

rt

rs

1011000

100

111

111

6

5

5

7

3

3

3

Format: 

PRECEU.PH.QBL rt, rs

DSP

Precision Expand Two Unsigned Bytes to Unsigned Halfword Values

Purpose:

Precision Expand Two Unsigned Bytes to Unsigned Halfword Values

Expand the precision of two unsigned byte values taken from the two left-most elements of a quad byte vector to create two unsigned halfword values.

Description: 

rt = expand_prec8u16(rs31..24) || expand_prec8u16(rs23..16)

The two left-most unsigned integer byte values from the four byte elements in register rs are expanded to create two unsigned halfword values that are then written to destination register rt. The precision expansion is achieved by prepending eight most-significant zeros to each original value to generate each 16 bit unsigned value.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

ValidateAccessToDSPResources()
tempB15..0 = 08 || GPR[rs]31..24
tempA15..0 = 08 || GPR[rs]23..16
GPR[rt]31..0 = tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled