Encoding:

Format:

MULEU_S.PH.QBR rd, rs, rt

Purpose:

Multiply Unsigned Vector Right Bytes with halfwords to Half Word Products

Element-wise multiplication of unsigned byte elements with corresponding unsigned halfword elements, with saturation.

Description:

rd = sat16(rs15..8 * rt31..16) || sat16(rs7..0 * rt15..0)

The two right-most unsigned byte elements in a four-element byte vector in register rs are multiplied as unsigned integer values with the corresponding right-most 16-bit unsigned values from register rt. Each result is clipped to preserve the 16 l east-significant bits and written back into the respective halfword element positions in the destination register rd. The instruction saturates the result to the maximum positive value (0xFFFF hexadecimal) if any of the clipped bits are non-zero.

To stay compliant with the base architecture, this instruction leaves the base HI/LO pair (accumulator ac0) UNPREDICTABLE after the operation completes. The other DSP Module accumulators, ac1, ac2, and ac3 must be unmodified.

This instruction writes a 1 to bit 21 in the ouflag field in the DSPControl register if either multiplication results in saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ValidateAccessToDSPResources()
tempB15..0 = multiplyU8U16( GPR[rs]15..8, GPR[rt]31..16 )
tempA15..0 = multiplyU8U16( GPR[rs]7..0, GPR[rt]15..0 )
GPR[rd] = tempB15..0 || tempA15..0
HI[0]31..0 = UNPREDICTABLE
LO[0]31..0 = UNPREDICTABLE

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The base MIPS32 architecture states that after a GPR-targeting multiply instruction such as MUL, the contents of registers HI and LO are UNPREDICTABLE. To maintain compliance with the base architecture this multiply instruction, MULEU_S.PH.QBR, has the same requirement. Software must save and restore the ac0 register if the previous value in the ac0 register is needed following the MULEU_S.PH.QBR instruction.

Note that the requirement on HI and LO does not apply to the new accumulator registers ac1, ac2, and ac3; as a result the values in these accumulators need not be saved.