P32A 001000 |
rt |
rs |
x |
x |
CMPU.EQ.QB 1001000 |
101 |
P32A 001000 |
rt |
rs |
x |
x |
CMPU.LE.QB 1011000 |
101 |
P32A 001000 |
rt |
rs |
x |
x |
CMPU.LT.QB 1010000 |
101 |
6 |
5 |
5 |
5 |
1 |
7 |
3 |
CMPU.cond.QB |
Compare Vectors of Unsigned Byte Values | |
CMPU.EQ.QB rs, rt |
DSP |
Compare Vectors of Unsigned Byte Values |
CMPU.LT.QB rs, rt |
DSP |
Compare Vectors of Unsigned Byte Values |
CMPU.LE.QB rs, rt |
DSP |
Compare Vectors of Unsigned Byte Values |
Compare Vectors of Unsigned Byte Values
Perform an element-wise comparison of two vectors of unsigned bytes, recording the results of the comparison in condition code bits.
DSPControlccond:27..24 = (rs31..24 cond rt31..24) || (rs23..16 cond rt23..16) || (rs15..8 cond rt15..8) || (rs7..0 cond rt7..0)
Each of the unsigned byte elements in register rs are compared with the corresponding unsigned byte elements in register rt. The four 1-bit boolean comparison results are written to bits 24 through 27 of the DSPControl register’s 4-bit condition code field.
No data-dependent exceptions are possible.
The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.
CMPU.EQ.QB ValidateAccessToDSPResources() ccD = GPR[rs]31..24 EQ GPR[rt]31..24 ccC = GPR[rs]23..16 EQ GPR[rt]23..16 ccB = GPR[rs]15..8 EQ GPR[rt]15..8 ccA = GPR[rs]7..0 EQ GPR[rt]7..0 DSPControlccond:27..24 = ccD || ccC || ccB || ccA CMPU.LT.QB ValidateAccessToDSPResources() ccD = GPR[rs]31..24 LT GPR[rt]31..24 ccC = GPR[rs]23..16 LT GPR[rt]23..16 ccB = GPR[rs]15..8 LT GPR[rt]15..8 ccA = GPR[rs]7..0 LT GPR[rt]7..0 DSPControlccond:27..24 = ccD || ccC || ccB || ccA CMPU.LE.QB ValidateAccessToDSPResources() ccB = GPR[rs]15..8 LE GPR[rt]15..8 ccA = GPR[rs]7..0 LE GPR[rt]7..0 DSPControlccond:27..24 = ccD || ccC || ccB || ccA
Reserved Instruction, DSP Disabled