Assembly:

GINVI rs

Purpose:

Globally Invalidate Instruction caches.

Availability:

nanoMIPS. Optional, present when

Config5.GI >= 2. Requires CP0 privilege.

Format:

Operation:

if C0.Config5.GI < 2:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if GPR[rs] == 0:
    cores = get_all_cores_in_system()
else:
    cores = implementation_dependent_ginvi_cores(GPR[rs])
for core in cores:
    # Find encoded line size, sets, and associativity for thetargetcache.
    (L, S, A) = get_cache_parameters('I', core)
    num_sets = 2 ** (S + 6)
    num_ways = A + 1
    for way_index in range(num_ways):
        for set_index in range(num_sets):
            cache_line = get_cache_line('I', way_index,set_index, core)
            cache_line.valid = False

When $rs is 0, GINVI fully invalidates allinstruction caches of all cores in the system,including the localinstruction cache. For non-zero $rs values, GINVI invalidates the instruction cache of a specific,

implementation dependent core in the system.

The GINVIinstruction must be followed by a SYNC (stype=0x14) and an instruction hazard barrier (e.g.JRC.HB) to ensure that all instruction caches in the system have been invalidated.

Exceptions:

Coprocessor Unusable. Reserved Instruction if Global Invalidate I-cache not implemented.