Assembly:

LHE rt, offset(rs)

Purpose:

Load Half using EVA addressing. Load signed halfword to register $rt from virtual address$rs + offset, translating the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege.

Format:

Operation:

if not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
offset = sign_extend(s, from_nbits=9)
va = effective_address(GPR[rs], offset, 'Load', eva=True)
data = read_memory_at_va(va, nbytes=2, eva=True)
GPR[rt] = sign_extend(data, from_nbits=16)

Exceptions:

Address Error. Bus Error. Coprocessor Unusable. Reserved Instruction if EVA not implemented. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.