Encoding:

Format:

PREPEND rt, rs, sa

EXTW rt, rs, rt, sa

Purpose:

Right Shift and Prepend Bits to the MSB

Logically right-shift the first source register, replacing the bits emptied by the shift with bits from the source register.

Description:

rt = rssa-1..0 || (rt >> sa)

The word value in register rt is logically right-shifted by the specified shift amount sa, and sa bits from the least-significant positions of register rs are written into the sa most-significant bits emptied by the shift. The result is then written to destination register rt.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ValidateAccessToDSP2Resources()
if ( sa4..0 = 0 ) then
   temp31..0 = GPR[rt]31..0 
else
   temp31..0 = ( GPR[rs]sa-1..0 || GPR[rt]31..sa )
endif
GPR[rt]31..0 = temp31..0

Exceptions:

Reserved Instruction, DSP Disabled