Encoding:

001000	rt	rs	sel	u	100011	h	000
6	5	5	5	1	6	1	3

Format:

MFTR rt, rs, u, sel, h

MIPS MT

Move from Thread Context

Purpose:

Move from Thread Context

To move the contents of a register within a targeted thread context or VPE into a general register of the current thread.

Description:

GPR[rt] = TC[VPEControl_TargTC][u,rs,sel,h]

The contents of the register specified are loaded into general register rt. The target context to be read is determined by the value of the TargTC field of the CP0 VPEControl register (see Section 6.5). The register to be read within the selected context is determined by the value in the rs operand register, in conjunction with the u and sel bits of the

MFTR instruction, according to table Table 5.1. If the register to be read is instantiated per-processor or per-VPE, rather than per-TC, the register selected is that of the processor within which the target TC is instantiated, or the VPE to which the target TC is bound (see Section 6.13), respectively.

Coprocessor 1 and 2 registers and DSP accumulators referenced by the MFTR instruction are those bound to the target TC. The TCUx bits and TMX bit of the target TC’s TCStatus register are ignored.

If the selected register is not implemented on the processor, or otherwise not accessible to the TC that issued the

MFTR, as in the case of references to TCs and coprocessor resources bound to other VPEs when the VPE executing the MFTR does not have MVP set in VPConfig0, the resulting rt value is -1.

Release 5 adds the instruction MFTHC0.

The Idiom(s) column in Table 5.1 specifies the assembler idiom that is used to express an access to the particular register.

The selected value is written into the target register rt. If the precision of the source register is less than the precision of the target GPR, the value is sign-extended.

The h bit of the instruction word selects the high-order half of the source register in instances where the source is a register of greater precision than the target GPR.

Restrictions:

An MFTR instruction where the target TC is not in a Halted state (i.e., TCHalt.H is not set), or where a TC other than the one issuing the MFTR is active in the target VPE on a reference to a per-VPE CP0 register, may result in an

If the target TC is blocked but not halted, then the thread issuing the MFTR instruction may be blocked indefinitely.

This is due to the target TC waiting on an external event that may never happen. It is recommended that the

TCStatus_RNST bit of the target TC be checked before issuing the MFTR instruction.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In any implementation with Floating-Point-Unit, if TCStatus_TFR is set so the effective FPR width matches the GPR width, a MFTR instruction targetting one of the FPRs with h=1 will cause UNPREDICTABLE results.

Operation:

if IsCoprocessorEnabled(0) then
   if VPEConf0_MVP = 0 and ( TC[VPEControl_TargTC].TCBind_CurVPE != TCBind_CurVPE) then
      data = -1
   else if VPEControl_TargTC > MVPConf0_PTC then
      data = -1
   else if u = 0 then
      data = TC[VPEControl_TargTC].CPR[0,rs,sel]
   else
      if h = 1 then
         topbit = 63
         bottombit = 32
      else
         topbit = 31
         bottombit = 0
      endif
      case sel
         0: data = TC[VPEControl_TargTC].GPR[rs]_{topbit..bottombit}
         1: case rs
             0: data = TC[VPEControl_TargTC].Lo
             1: data = TC[VPEControl_TargTC].Hi
             2: data = TC[VPEControl_TargTC].ACX
             4: data = TC[VPEControl_TargTC].DSPLo[1]
             5: data = TC[VPEControl_TargTC].DSPHi[1]
             6: data = TC[VPEControl_TargTC].DSPACX[1]
             8: data = TC[VPEControl_TargTC].DSPLo[2]
             9: data = TC[VPEControl_TargTC].DSPHI[2]
             10:data = TC[VPEControl_TargTC].DSPACX[2]
             12 data = TC[VPEControl_TargTC].DSPLo[3]
             13:data = TC[VPEControl_TargTC].DSPHi[3]
             14:data = TC[VPEControl_TargTC].DSPACX[3]
             16:data = TC[VPEControl_TargTC].DSPControl
             otherwise: data = UNPREDICTABLE
             2: if ( ( Config_AT = 0 and Status_FR = 0) or 
                     ( Config_AT = 1 or Config_AT = 2) )
                   // GPR and FPR widths match
                   if (h = 0 ) 
                       data = TC[VPEControl_TargTC].FPR[rs]
                   else
                       UNPREDICTABLE
                   endif
                elseif (Config_AT = 0 and Status_FR = 1)
                    // 32-bit GPRs and 64-bit FPRs
                    data = TC[VPEControl_TargTC].FPR[rs]_{topbit..bottombit}
                endif
         3: data = TC[VPEControl_TargTC].FPCR[rs]
         4: data = TC[VPEControl_TargTC].CP2CPR[rx||rs]_{topbit..bottombit}
         5: data = TC[VPEControl_TargTC].CP2CCR[rx||rs]_{topbit..bottombit}
         otherwise: data = UNPREDICTABLE
   if h = 1 then
      data = data_63..32
   endif
   GPR[rt] = data_31..0
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction