GINVT rs, type - Globally invalidate TLBs

Assembly:

GINVT rs, type

nanoMIPS. Optional, present when Config5.GI=3. Requires CP0 privilege.

Globally invalidate TLBs

Purpose:

Globally invalidate TLBs.

Availability:

nanoMIPS. Optional, present when Config5.GI=3. Requires CP0 privilege.

Format:

001000	x	type	rs	00	00111	101	111	111
6	3	2	5	2	5	3	3	3

Operation:

if C0.Config5.GI != 3:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if not C0.Config5.MI:
    raise exception('RI', 'Config5.MI notset')
ginvt(type, va=GPR[rs])

Perform type invalidation of all TLBs in the system, where type is one of:

```
     type=0:
```

invALL - invalidate all non wired entries.

```
     type=1:
```

invVA- invalidate all entries which match the VA speciﬁed by $rs.

```
     type=2:
```

invMMID invalidate all entries which match C0.MemoryMapID.MMID and are not

global.

```
     type=3:
```

invVAMMID - invalidate all entries which match the VA speciﬁed by $rs and either match

C0.MemoryMapID or are global.

The GINVT instruction must be followed by a SYNC (stype=0x14) and an instruction hazard barrier (e.g.JRC.HB) to ensure that matching entries have been removed from all TLBs in the system and that

all instructions in the instruction stream can only access the new context.

invMMID and invVAMMID operations use the C0.MemoryMapID value of the currently running process. The kernel must save/restore C0.MemoryMapID appropriately before it modiﬁes it for the invalidation

operation. Between the save and restore, it must utilize unmapped addresses.

Exceptions:

Coprocessor Unusable.Reserved Instruction if GlobalInvalidate TLB notimplemented.Reserved Instruction if MemoryMapID not enabled (i.e. Conﬁg5.MI==0).