LHUX rd, rs(rt) |
nanoMIPS |
Load Half Unsigned indeXed |
Load Half Unsigned indeXed. Load unsigned halfword to register $rd from memory address$rt + $rs (register plus register).
nanoMIPS
|
001000 |
rt |
rs |
rd |
0110 |
0 |
000 |
111 |
|
6 |
5 |
5 |
5 |
4 |
1 |
3 |
3 |
va = effective_address(GPR[rs], GPR[rt], 'Load') GPR[rd] = read_memory_at_va(va, nbytes=2)
Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.