Assembly:

SWM rt, offset(rs), count

Purpose:

Store Word Multiple.Storecount wordsofdatafrom registers$rt, $(rt+1),...,

$(rt+count-1) to consecutive memory addressesstarting at $rs + offset (register plusimmediate).

Availability:

nanoMIPS, not available in NMS

Format:

offset = sign_extend(s, from_nbits=9)
count = 8 if count3 == 0 else count3

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
i = 0
while i != count:
    this_rt = ( 0           if rt == 0    else
                rt + i      if rt + i < 32 else
                rt + i - 16                    )
    this_offset = offset + (i<<2)
    va = effective_address(GPR[rs], this_offset, 'Store')
    data = zero_extend(GPR[this_rt], from_nbits=32)
    write_memory_at_va(data, va, nbytes=4)
    i += 1

SWM stores count words from sequentially numbered registers to sequential memory addresses. After storing $31, the sequence of registers continues from $16.If rt=0, then $0 is stored for all count steps

of the instruction. Some example encodings of the register list are:

• rt=15, count=3:

loads [$15, $16, $17]

• rt=31, count=3: saves [$31, $16, $17]

• rt=0, count=3: saves [$0, $0, $0].

If a TLB exception or interrupt occurs during the execution of this instruction, a subset of the required memory updates may have occurred. A full restart of the instruction will be performed on return from

the exception.

Exceptions:

Address Error. Bus Error. Reserved Instruction on NMS cores. TLB Invalid. TLB Modified. TLB Refill. Watch.