Assembly:

SYNCI  offset(rs)

SYNCIE offset(rs)

Purpose:

SYNChronize Instruction cache/SYNChronize Instruction cache using EVA addressing. Synchronize the caches to make instructions writes at address $rs + offset (register plus immediate) effective. For SYNCIE, translate the virtual address as though the core is in user mode, although it is

actually in kernel mode.

Availability:

nanoMIPS, availability varies by format.

Format:

SYNCI[S9]

offset = sign_extend(s, from_nbits=9)
is_eva = False

SYNCI[U12]

offset = u
is_eva = False

SYNCIE, present when Config5.EVA=1, requires CP0 privilege.

offset = sign_extend(s, from_nbits=9)
is_eva = True

Operation:

if is_eva and not C0.Config5.EVA:
    raise exception('RI')
if is_eva and not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=is_eva)
pa, cca = va2pa(va, 'Cacheop', eva=is_eva)
# Make data writes at address=PA visible to the instructionstream(forall
# coherent cores in the system)...
# The precise details of the operation are implementationdependent,andwill
# depend on the cache hierarchy and coherency behaviorofthesystem.The
# following code shows a sample implementation forasystemwherethememory
# hierarchy is unified beyond the L1 instruction anddatacaches.
# Find index where address is present in D cache, ifany.
dcache_hit_index = cache_lookup_index('D', va, pa)
if dcache_hit_index:
    way_index, set_index = dcache_hit_index
    dcache_line = get_cache_line('D',way_index, set_index)
    if dcache_line.valid and dcache_line.dirty:
        dcache_line.write_back()
        # Implementation may or may not invalidateline too,seebelow.
for core in get_all_cores_in_system():
    # Find index where address is presentin this core'sIcache,ifany.
    icache_hit_index = cache_lookup_index('I', va, pa, core)
    if icache_hit_index:
        way_index, set_index = icache_hit_index
        icache_line = get_cache_line('I', way_index, set_index,core)
        if not icache_line.locked:
            icache_line.valid = 0

SYNCI is a user privilege instruction for synchronizing the caches to make instruction writes to address

$rs + offset effective. SYNCI must be followed by a SYNC instruction and an instruction hazard barrier to guarantee that subsequent instruction fetches see the updated instructions. One SYNCI instruction

is required for every cache line that was written. The size of the cache line can be determined by the RDHWR instruction.

SYNCI can cause TLB Refill and TLB invalid exceptions (with cause code TLBL). It does not cause TLBRI exceptions. A Cache Error or Bus Error exception may occur as a result of a writeback triggered by

the instruction.

An Address Error Exception (with cause code equal ADEL) may occur if a SYNCI targets an address which is not accessible from the current operating mode.It is implementation dependent whether such

an exception does occur, but the instruction should not affect cache lines which are not accessible from the current operating mode.

It is implementation dependent whether a data watch exception is triggered by a SYNCI instruction whose address matches the Watch register address match conditions. The preferred implementation

is not to match on the SYNCI instruction.

The operation of the processor is UNPREDICTABLE if the effective address of the SYNCI targets any instruction cache line that contains instructions to be executed between the SYNCI and the subsequent

JALRC.HB, JRC.HB, or ERET instruction required to clear the instruction hazard.

The SYNCIinstruction has no effect on cache lines that were previously locked with the CACHE instruction.

If correct software operation depends on the state of a locked line, the CACHE instruction

must be used to synchronize the caches.

In multi-processor systems, a SYNCI to an address with a coherent CCA must guarantee synchronization of all coherent instruction caches in the system.

(Prior to Release 6 of the MIPS™ Architecture,

this behavior was recommended but not required).

The manner in which SYNCI is implemented will depend on the cache hierarchy of the processor. Typically, all caches out

to the point at which both instruction and data references become unified are

processed.If no caches exist or if instruction cache coherency is already guaranteed, the instruction must be implemented as a NOP.

In a typical implementation in which only the L1 instruction and data caches are affected, this instruction would perform a Hit

Invalidate operation on the instruction cache and a Hit Writeback or Hit

Writeback Invalidate on the data cache. The decision to invalidate the data cache line is implementation dependent, but should be made under the assumption that the data will not be written again soon.

If a Hit Writeback Invalidate (as opposed to a Hit Writeback) would cause the line to be selected for replacement, the invalidate option might be selected.

The following example shows a routine which could be called after the new instruction stream is written to make those changes effective.

/*
 * This routine makes changes to the instruction stream effectivetothe
 * hardware. It should be called after the instruction streamiswritten.
 * On return, the new instructions are effective.
 *
 * Inputs:
 *   a0 = Start address of new instruction stream
 *   a1 = Size in bytes of new instructionstream
 */
        beqc    a1, zero, 20f     /* If size==0, branch around. */
        addu    a1, a0, a1        /* Calculateendaddress+ 1. */
        rdhwr   v0, HW_SYNCI_Step /* Get step sizeforSYNCI. */
        beqc    v0, zero, 20f     /* Nothing to doif no caches. */
10:     synci   0(a0)             /* Sync allcachesaroundaddress. */
        addu    a0, a0, v0        /* Addstepsize.*/
        sltu    v1, a0, a1        /* Notpastthe endaddress? */
        bnec    v1, zero, 10b     /* Branchif moreto do. */
        sync                      /* Clear memory hazards.*/
20:     jrc.hb ra                /* Return, clearinginstruction hazards. */

Exceptions:

Address Error. Bus Error. Cache Error. Coprocessor Unusable for SYNCIE. Reserved Instruction for SYNCIE if EVA not implemented. TLB Invalid. TLB Refill.