AVR32 ISA Reference |
|
32000D-04/2011 |
|
abs Rd |
Rev1+ |
Absolute Value |
|
acall disp |
Rev1+ |
Application Call |
|
acr Rd |
Rev1+ |
Add Carry to Register |
|
adc Rd, Rx, Ry |
Rev1+ |
Add with Carry |
|
add Rd, Rs |
Rev1+ |
Add without Carry |
|
add Rd, Rx, Ry << sa |
Rev1+ |
Add without Carry |
|
addabs Rd, Rx, Ry |
Rev1+ |
Add Absolute Value |
|
addhh.wRd, Rx:<part>, Ry:<part> |
Rev1+ |
Add Halfwords into Word |
|
add{cond4}Rd, Rx, Ry |
Rev2+ |
Conditional Add |
|
and Rd, Rs |
Rev1+ |
Logical AND with optional logical shift |
|
and Rd, Rx, Ry << sa |
Rev1+ |
Logical AND with optional logical shift |
|
and Rd, Rx, Ry >> sa |
Rev1+ |
Logical AND with optional logical shift |
|
andh Rd, imm |
Rev1+ |
Logical AND into high or low half of register |
|
andh Rd, imm, COH |
Rev1+ |
Logical AND into high or low half of register |
|
andl Rd, imm |
Rev1+ |
Logical AND into high or low half of register |
|
andl Rd, imm, COH |
Rev1+ |
Logical AND into high or low half of register |
|
andn Rd, Rs |
Rev1+ |
Logical AND NOT |
|
and{cond4}Rd, Rx, Ry |
Rev2+ |
Conditional And |
|
asr Rd, Rx, Ry |
Rev1+ |
Arithmetic Shift Right |
|
asr Rd, sa |
Rev1+ |
Arithmetic Shift Right |
|
asr Rd, Rs, sa |
Rev1+ |
Arithmetic Shift Right |
|
bfexts Rd, Rs, bp5, w5 |
Rev1+ |
Bitfield extract and sign-extend |
|
bfextu Rd, Rs, bp5, w5 |
Rev1+ |
Bitfield extract and zero-extend |
|
bfins Rd, Rs, bp5, w5 |
Rev1+ |
Bitfield insert |
|
bld Rd, bp |
Rev1+ |
Bit load from register to C and Z |
|
breakpoint |
Rev1+ |
Software Debug Breakpoint |
|
brev Rd |
Rev1+ |
Bit Reverse |
|
br{cond3}disp |
Rev1+ |
Branch if Condition Satisfied |
|
br{cond4}disp |
Rev1+ |
Branch if Condition Satisfied |
|
bst Rd, bp |
Rev1+ |
Copy C to register bit |
|
cache Rp[disp], Op5 |
Rev1+ |
Perform Cache control operation |
|
casts.h Rd |
Rev1+ |
Typecast to Signed Word |
|
casts.b Rd |
Rev1+ |
Typecast to Signed Word |
|
castu.h Rd |
Rev1+ |
Typecast to Unsigned Word |
|
castu.b Rd |
Rev1+ |
Typecast to Unsigned Word |
|
cbr Rd, bp |
Rev1+ |
Clear Bit in Register |
|
clz Rd, Rs |
Rev1+ |
Count Leading Zeros |
|
com Rd |
Rev1+ |
One’s Compliment |
|
cop CP#, CRd, CRx, CRy, Op |
Rev1+ |
Coprocessor Operation |
|
cp.b Rd, Rs |
Rev1+ |
Compare Byte |
|
cp.h Rd, Rs |
Rev1+ |
Compare Halfword |
|
cp.w Rd, Rs |
Rev1+ |
Compare Word |
|
cp.w Rd, imm |
Rev1+ |
Compare Word |
|
cp.w Rd, imm |
Rev1+ |
Compare Word |
|
cpc Rd, Rs |
Rev1+ |
Compare with Carry |
|
cpc Rd |
Rev1+ |
Compare with Carry |
|
csrf bp |
Rev1+ |
Clear Status Register Flag |
|
csrfcz bp |
Rev1+ |
Copy Status Register Flag to C and Z |
|
divs Rd, Rx, Ry |
Rev1+ |
Signed divide |
|
divu Rd, Rx, Ry |
Rev1+ |
Unsigned divide |
|
eor Rd, Rs |
Rev1+ |
Logical Exclusive OR with optional logical shift |
|
eor Rd, Rx, Ry << sa |
Rev1+ |
Logical Exclusive OR with optional logical shift |
|
eor Rd, Rx, Ry >> sa |
Rev1+ |
Logical Exclusive OR with optional logical shift |
|
eorh Rd, imm |
Rev1+ |
Logical EOR into high or low half of register |
|
eorl Rd, imm |
Rev1+ |
Logical EOR into high or low half of register |
|
eor{cond4} Rd, Rx, Ry |
Rev2+ |
Conditional Logical EOR |
|
frs |
Rev1+ |
Flush Return Stack |
|
icall Rd |
Rev1+ |
Indirect Call to Subroutine |
|
incjosp imm |
Rev1+ |
Increment Java Operand Stack Pointer |
|
ld.d Rd, Rp++ |
Rev1+ |
Load Doubleword |
|
ld.d Rd, --Rp |
Rev1+ |
Load Doubleword |
|
ld.d Rd, Rp |
Rev1+ |
Load Doubleword |
|
ld.d Rd, Rp[disp] |
Rev1+ |
Load Doubleword |
|
ld.d Rd, Rb[Ri<<sa] |
Rev1+ |
Load Doubleword |
|
ld.sb Rd, Rp[disp] |
Rev1+ |
Load Sign-extended Byte |
|
ld.sb Rd, Rb[Ri<<sa] |
Rev1+ |
Load Sign-extended Byte |
|
ld.sb{cond4} Rd, Rp[disp] |
Rev2+ |
Conditionally Load Sign-extended Byte |
|
ld.sh Rd, Rp++ |
Rev1+ |
Load Sign-extended Halfword |
|
ld.sh Rd, --Rp |
Rev1+ |
Load Sign-extended Halfword |
|
ld.sh Rd, Rp[disp] |
Rev1+ |
Load Sign-extended Halfword |
|
ld.sh Rd, Rp[disp] |
Rev1+ |
Load Sign-extended Halfword |
|
ld.sh Rd, Rb[Ri<<sa] |
Rev1+ |
Load Sign-extended Halfword |
|
ld.sh{cond4} Rd, Rp[disp] |
Rev2+ |
Conditionally Load Sign-extended Halfword |
|
ld.ub Rd, Rp++ |
Rev1+ |
Load Zero-extended Byte |
|
ld.ub Rd, --Rp |
Rev1+ |
Load Zero-extended Byte |
|
ld.ub Rd, Rp[disp] |
Rev1+ |
Load Zero-extended Byte |
|
ld.ub Rd, Rp[disp] |
Rev1+ |
Load Zero-extended Byte |
|
ld.ub Rd, Rb[Ri<<sa] |
Rev1+ |
Load Zero-extended Byte |
|
ld.ub{cond4} Rd, Rp[disp] |
Rev2+ |
Conditionally Load Zero-extended Byte |
|
ld.uh Rd, Rp++ |
Rev1+ |
Load Zero-extended Halfword |
|
ld.uh Rd, --Rp |
Rev1+ |
Load Zero-extended Halfword |
|
ld.uh Rd, Rp[disp] |
Rev1+ |
Load Zero-extended Halfword |
|
ld.uh Rd, Rp[disp] |
Rev1+ |
Load Zero-extended Halfword |
|
ld.uh Rd, Rb[Ri<<sa] |
Rev1+ |
Load Zero-extended Halfword |
|
ld.uh{cond4} Rd, Rp[disp] |
Rev2+ |
Conditionally Load Zero-extended Halfword |
|
ld.w Rd, Rp++ |
Rev1+ |
Load Word |
|
ld.w Rd, --Rp |
Rev1+ |
Load Word |
|
ld.w Rd, Rp[disp] |
Rev1+ |
Load Word |
|
ld.w Rd, Rp[disp] |
Rev1+ |
Load Word |
|
ld.w Rd, Rb[Ri<<sa] |
Rev1+ |
Load Word |
|
ld.w Rd, Rb[Ri:<part> << 2] |
Rev1+ |
Load Word |
|
ld.w{cond4} Rd, Rp[disp] |
Rev2+ |
Conditionally Load Word |
|
ldc.d CP#, CRd, Rp[disp] |
Rev1+ |
Load Coprocessor |
|
ldc.d CP#, CRd, --Rp |
Rev1+ |
Load Coprocessor |
|
ldc.d CP#, CRd, Rb[Ri<<sa] |
Rev1+ |
Load Coprocessor |
|
ldc.w CP#, CRd, Rp[disp] |
Rev1+ |
Load Coprocessor |
|
ldc.w CP#, CRd, --Rp |
Rev1+ |
Load Coprocessor |
|
ldc.w CP#, CRd, Rb[Ri<<sa] |
Rev1+ |
Load Coprocessor |
|
ldc0.d CRd, Rp[disp] |
Rev1+ |
Load Coprocessor 0 |
|
ldc0.w CRd, Rp[disp] |
Rev1+ |
Load Coprocessor 0 |
|
ldcm.d CP#, Rp{++}, ReglistCPD8 |
Rev1+ |
Load Coprocessor Multiple Registers |
|
ldcm.w CP#, Rp{++}, ReglistCPH8 |
Rev1+ |
Load Coprocessor Multiple Registers |
|
ldcm.w CP#, Rp{++}, ReglistCPL8 |
Rev1+ |
Load Coprocessor Multiple Registers |
|
lddpc Rd, PC[disp] |
Rev1+ |
Load PC-relative with Displacement |
|
lddsp Rd, SP[disp] |
Rev1+ |
Load SP-relative with Displacement |
|
ldins.b Rd:<part>, Rp[disp] |
Rev1+ |
Load and Insert Byte or Halfword into register |
|
ldins.h Rd:<part>, Rp[disp] |
Rev1+ |
Load and Insert Byte or Halfword into register |
|
ldm Rp{++}, Reglist16 |
Rev1+ |
Load Multiple Registers |
|
ldmts Rp{++}, Reglist16 |
Rev1+ |
Load Multiple Registers for Task Switch |
|
ldswp.shRd, Rp[disp] |
Rev1+ |
Load and Swap |
|
ldswp.uhRd, Rp[disp] |
Rev1+ |
Load and Swap |
|
ldswp.wRd, Rp[disp] |
Rev1+ |
Load and Swap |
|
lsl Rd, Rx, Ry |
Rev1+ |
Logical Shift Left |
|
lsl Rd, sa |
Rev1+ |
Logical Shift Left |
|
lsl Rd, Rs, sa |
Rev1+ |
Logical Shift Left |
|
lsr Rd, Rx, Ry |
Rev1+ |
Logical Shift Right |
|
lsr Rd, sa |
Rev1+ |
Logical Shift Right |
|
lsr Rd, Rs, sa |
Rev1+ |
Logical Shift Right |
|
mac Rd, Rx, Ry |
Rev1+ |
Multiply Accumulate |
|
machh.d Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply Halfwords and Accumulate in Doubleword |
|
machh.w Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply Halfwords and Accumulate in Word |
|
macs.d Rd, Rx, Ry |
Rev1+ |
Multiply Accumulate Signed |
|
macsathh.w Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply-Accumulate Halfwords with Saturation into Word |
|
macu.d Rd, Rx, Ry |
Rev1+ |
Multiply Accumulate Unsigned |
|
macwh.d Rd, Rx, Ry:<part> |
Rev1+ |
Multiply Word with Halfword and Accumulate in Doubleword |
|
max Rd, Rx, Ry |
Rev1+ |
Return Maximum Value |
|
mcall Rp[disp] |
Rev1+ |
Subroutine Call |
|
memc imm, bp5 |
Rev1+ |
Clear bit in memory |
|
mems imm, bp5 |
Rev1+ |
Set bit in memory |
|
memt imm, bp5 |
Rev1+ |
Toggle bit in memory |
|
mfdr Rd, DebugRegisterNo |
Rev1+ |
Move from Debug Register |
|
mfsr Rd, SystemRegisterAddress |
Rev1+ |
Move from System Register |
|
min Rd, Rx, Ry |
Rev1+ |
Return Minimum Value |
|
mov Rd, imm |
Rev1+ |
Move Data Into Register |
|
mov Rd, imm |
Rev1+ |
Move Data Into Register |
|
mov Rd, Rs |
Rev1+ |
Move Data Into Register |
|
movh Rd, imm |
Rev2+ |
Move Data Into High Halfword of Register |
|
mov{cond4} Rd, Rs |
Rev1+ |
Conditional Move Register |
|
mov{cond4} Rd, imm |
Rev1+ |
Conditional Move Register |
|
mtdr DebugRegisterAddress, Rs |
Rev1+ |
Move to Debug Register |
|
mtsr SystemRegisterAddress, Rs |
Rev1+ |
Move to System Register |
|
mul Rd, Rs |
Rev1+ |
Multiply |
|
mul Rd, Rx, Ry |
Rev1+ |
Multiply |
|
mul Rd, Rs, imm |
Rev1+ |
Multiply |
|
mulhh.w Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply Halfword with Halfword |
|
mulnhh.w Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply Halfword with Negated Halfword |
|
mulnwh.d Rd, Rx, Ry:<part> |
Rev1+ |
Multiply Word with Negated Halfword |
|
muls.d Rd, Rx, Ry |
Rev1+ |
Multiply Signed |
|
mulsathh.h Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply Halfwords with Saturation into Halfword |
|
mulsathh.w Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply Halfwords with Saturation into Word |
|
mulsatrndhh.h Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Multiply Halfwords with Saturation and Rounding into |
|
mulsatrndwh.w Rd, Rx, Ry:<part> |
Rev1+ |
Multiply Word and Halfword with Saturation and |
|
mulsatwh.w Rd, Rx, Ry:<part> |
Rev1+ |
Multiply Word and Halfword with Saturation into Word |
|
mulu.d Rd, Rx, Ry |
Rev1+ |
Multiply Unsigned |
|
mulwh.d Rd, Rx, Ry:<part> |
Rev1+ |
Multiply Word with Halfword |
|
musfr Rs |
Rev1+ |
Copy Register to Status Register |
|
mustr Rd |
Rev1+ |
Copy Status Register to Register |
|
mvcr.d CP#, Rd, CRs |
Rev1+ |
Move Coprocessor Register to Register file |
|
mvcr.w CP#, Rd, CRs |
Rev1+ |
Move Coprocessor Register to Register file |
|
mvrc.d CP#, CRd, Rs |
Rev1+ |
Move Register file Register to Coprocessor Register |
|
mvrc.w CP#, CRd, Rs |
Rev1+ |
Move Register file Register to Coprocessor Register |
|
neg Rd |
Rev1+ |
Two’s Complement |
|
nop |
Rev1+ |
No Operation |
|
or Rd, Rs |
Rev1+ |
Logical OR with optional logical shift |
|
or Rd, Rx, Ry << sa |
Rev1+ |
Logical OR with optional logical shift |
|
or Rd, Rx, Ry >> sa |
Rev1+ |
Logical OR with optional logical shift |
|
orh Rd, imm |
Rev1+ |
Logical OR into high or low half of register |
|
orl Rd, imm |
Rev1+ |
Logical OR into high or low half of register |
|
or{cond4} Rd, Rx, Ry |
Rev2+ |
Conditional logical OR |
|
pabs.sb Rd, Rs |
Rev1+ |
Packed absolute value |
|
pabs.sh Rd, Rs |
Rev1+ |
Packed absolute value |
|
packsh.ub Rd, Rx, Ry |
Rev1+ |
Pack Signed Halfwords to Bytes |
|
packsh.sb Rd, Rx, Ry |
Rev1+ |
Pack Signed Halfwords to Bytes |
|
packw.sh Rd, Rx, Ry |
Rev1+ |
Pack Words to Signed Halfwords |
|
padd.b Rd, Rx, Ry |
Rev1+ |
Packed Addition |
|
padd.h Rd, Rx, Ry |
Rev1+ |
Packed Addition |
|
paddh.ub Rd, Rx, Ry |
Rev1+ |
Packed Addition with Halving |
|
paddh.sh Rd, Rx, Ry |
Rev1+ |
Packed Addition with Halving |
|
padds.ub Rd, Rx, Ry |
Rev1+ |
Packed Addition with Saturation |
|
padds.sb Rd, Rx, Ry |
Rev1+ |
Packed Addition with Saturation |
|
padds.uh Rd, Rx, Ry |
Rev1+ |
Packed Addition with Saturation |
|
padds.sh Rd, Rx, Ry |
Rev1+ |
Packed Addition with Saturation |
|
paddsub.h Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Halfword Addition and Subtraction |
|
paddsubh.sh Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Halfword Addition and Subtraction with Halving |
|
paddsubs.uh Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Halfword Addition and Subtraction with Sat- |
|
paddsubs.sh Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Halfword Addition and Subtraction with Sat- |
|
paddx.h Rd, Rx, Ry |
Rev1+ |
Packed Halfword Addition with Crossed Operand |
|
paddxh.sh Rd, Rx, Ry |
Rev1+ |
Packed Signed Halfword Addition with Crossed Operand |
|
paddxs.uh Rd, Rx, Ry |
Rev1+ |
Packed Halfword Addition with Crossed Operand and |
|
paddxs.sh Rd, Rx, Ry |
Rev1+ |
Packed Halfword Addition with Crossed Operand and |
|
pasr.b Rd, Rs, sa |
Rev1+ |
Packed Arithmetic Shift Right |
|
pasr.h Rd, Rs, sa |
Rev1+ |
Packed Arithmetic Shift Right |
|
pavg.ub Rd, Rx, Ry |
Rev1+ |
Packed Average |
|
pavg.sh Rd, Rx, Ry |
Rev1+ |
Packed Average |
|
plsl.b Rd, Rs, sa |
Rev1+ |
Packed Logical Shift Left |
|
plsl.h Rd, Rs, sa |
Rev1+ |
Packed Logical Shift Left |
|
plsr.b Rd, Rs, sa |
Rev1+ |
Packed Logical Shift Right |
|
plsr.h Rd, Rs, sa |
Rev1+ |
Packed Logical Shift Right |
|
pmax.ub Rd, Rx, Ry |
Rev1+ |
Packed Maximum Value |
|
pmax.sh Rd, Rx, Ry |
Rev1+ |
Packed Maximum Value |
|
pmin.ub Rd, Rx, Ry |
Rev1+ |
Packed Minimum Value |
|
pmin.sh Rd, Rx, Ry |
Rev1+ |
Packed Minimum Value |
|
popjc |
Rev1+ |
Pop Java Context from Frame |
|
popm Reglist8 {, R12 = {-1, 0, 1}} |
Rev1+ |
Pop Multiple Registers from Stack |
|
pref Rp[disp] |
Rev1+ |
Cache Prefetch |
|
psad Rd, Rx, Ry |
Rev1+ |
Packed Sum of Absolute Differences |
|
psub.b Rd, Rx, Ry |
Rev1+ |
Packed Subtraction |
|
psub.h Rd, Rx, Ry |
Rev1+ |
Packed Subtraction |
|
psubadd.h Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Halfword Subtraction and Addition |
|
psubaddh.sh Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Signed Halfword Subtraction and Addition with |
|
psubadds.uh Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Halfword Subtraction and Addition with |
|
psubadds.sh Rd, Rx:<part>, Ry:<part> |
Rev1+ |
Packed Halfword Subtraction and Addition with |
|
psubh.ub Rd, Rx, Ry |
Rev1+ |
Packed Subtraction with Halving |
|
psubh.sh Rd, Rx, Ry |
Rev1+ |
Packed Subtraction with Halving |
|
psubs.ub Rd, Rx, Ry |
Rev1+ |
Packed Subtraction with Saturation |
|
psubs.sb Rd, Rx, Ry |
Rev1+ |
Packed Subtraction with Saturation |
|
psubs.uh Rd, Rx, Ry |
Rev1+ |
Packed Subtraction with Saturation |
|
psubs.sh Rd, Rx, Ry |
Rev1+ |
Packed Subtraction with Saturation |
|
psubx.h Rd, Rx, Ry |
Rev1+ |
Packed Halfword Subtraction with Crossed Operand |
|
psubxh.sh Rd, Rx, Ry |
Rev1+ |
Packed Signed Halfword Subtraction with Crossed Operand |
|
psubxs.uh Rd, Rx, Ry |
Rev1+ |
Packed Halfword Subtraction with Crossed Operand |
|
psubxs.sh Rd, Rx, Ry |
Rev1+ |
Packed Halfword Subtraction with Crossed Operand |
|
punpckub.h Rd, Rs:<part> |
Rev1+ |
Unpack bytes to halfwords |
|
punpcksb.h Rd, Rs:<part> |
Rev1+ |
Unpack bytes to halfwords |
|
pushjc |
Rev1+ |
Push Java Context to Frame |
|
pushm Reglist8 |
Rev1+ |
Push Multiple Registers to Stack |
|
rcall PC[disp] |
Rev1+ |
Relative Subroutine Call |
|
rcall PC[disp] |
Rev1+ |
Relative Subroutine Call |
|
retd |
Rev1+ |
Return from Debug mode |
|
RETE |
Rev1+ |
Return from event handler |
|
retj |
Rev1+ |
Return from Java trap |
|
RETS |
Rev1+ |
Return from supervisor call |
|
RETSS |
Rev3+ |
Return from Secure State |
|
ret{cond4} Rs |
Rev1+ |
Conditional Return from Subroutine |
|
rjmp PC[disp] |
Rev1+ |
Relative Jump |
|
rol Rd |
Rev1+ |
Rotate Left through Carry |
|
ror Rd |
Rev1+ |
Rotate Right through Carry |
|
rsub Rd, Rs |
Rev1+ |
Reverse Subtract |
|
rsub Rd, Rs, imm |
Rev1+ |
Reverse Subtract |
|
rsub{cond4} Rd, imm |
Rev2+ |
Conditional Reverse Subtract |
|
satadd.hRd, Rx, Ry |
Rev1+ |
Saturated Add of Halfwords |
|
satadd.wRd, Rx, Ry |
Rev1+ |
Saturated Add of Words |
|
satrnds Rd >> sa, bp |
Rev1+ |
Saturate with Rounding Signed |
|
satrndu Rd >> sa, bp |
Rev1+ |
Saturate with Rounding Unsigned |
|
sats Rd >> sa, bp |
Rev1+ |
Saturate Signed |
|
satsub.hRd, Rx, Ry |
Rev1+ |
Saturated Subtract of Halfwords |
|
satsub.w Rd, Rx, Ry |
Rev1+ |
Saturated Subtract of Words |
|
satsub.w Rd, Rs, imm |
Rev1+ |
Saturated Subtract of Words |
|
satu Rd >> sa, bp |
Rev1+ |
Saturate Unsigned |
|
sbc Rd, Rx, Ry |
Rev1+ |
Subtract with Carry |
|
sbr Rd, bp |
Rev1+ |
Set Bit in Register |
|
scall |
Rev1+ |
Supervisor Call |
|
scr Rd |
Rev1+ |
Subtract Carry from Register |
|
sleep Op8 |
Rev1+ |
Set CPU Activity Mode |
|
sr{cond4} Rd |
Rev1+ |
Set Register Conditionally |
|
sscall |
Rev3+ |
Secure State Call |
|
ssrf bp |
Rev1+ |
Set Status Register Flag |
|
st.b Rp++, Rs |
Rev1+ |
Store Byte |
|
st.b --Rp, Rs |
Rev1+ |
Store Byte |
|
st.b Rp[disp], Rs |
Rev1+ |
Store Byte |
|
st.b Rp[disp], Rs |
Rev1+ |
Store Byte |
|
st.b Rb[Ri << sa], Rs |
Rev1+ |
Store Byte |
|
st.b{cond4} Rp[disp], Rs |
Rev2+ |
Conditionally Store Byte |
|
st.d Rp++, Rs |
Rev1+ |
Store Doubleword |
|
st.d --Rp, Rs |
Rev1+ |
Store Doubleword |
|
st.d Rp, Rs |
Rev1+ |
Store Doubleword |
|
st.d Rp[disp], Rs |
Rev1+ |
Store Doubleword |
|
st.d Rb[Ri << sa], Rs |
Rev1+ |
Store Doubleword |
|
st.h Rp++, Rs |
Rev1+ |
Store Halfword |
|
st.h --Rp, Rs |
Rev1+ |
Store Halfword |
|
st.h Rp[disp], Rs |
Rev1+ |
Store Halfword |
|
st.h Rp[disp], Rs |
Rev1+ |
Store Halfword |
|
st.h Rb[Ri << sa], Rs |
Rev1+ |
Store Halfword |
|
st.h{cond4} Rp[disp], Rs |
Rev2+ |
Conditionally Store Halfword |
|
st.w Rp++, Rs |
Rev1+ |
Store Word |
|
st.w --Rp, Rs |
Rev1+ |
Store Word |
|
st.w Rp[disp], Rs |
Rev1+ |
Store Word |
|
st.w Rp[disp], Rs |
Rev1+ |
Store Word |
|
st.w Rb[Ri << sa], Rs |
Rev1+ |
Store Word |
|
st.w{cond4} Rp[disp], Rs |
Rev2+ |
Conditionally Store Word |
|
stc.d CP#, Rp[disp], CRs |
Rev1+ |
Store Coprocessor |
|
stc.d CP#, Rp++, CRs |
Rev1+ |
Store Coprocessor |
|
stc.d CP#, Rb[Ri<<sa], CRs |
Rev1+ |
Store Coprocessor |
|
stc.w CP#, Rp[disp], CRs |
Rev1+ |
Store Coprocessor |
|
stc.w CP#, Rp++, CRs |
Rev1+ |
Store Coprocessor |
|
stc.w CP#, Rb[Ri<<sa], CRs |
Rev1+ |
Store Coprocessor |
|
stc0.d Rp[disp], CRs |
Rev1+ |
Store Coprocessor 0 Register |
|
stc0.w Rp[disp], CRs |
Rev1+ |
Store Coprocessor 0 Register |
|
stcm.d CP#, {--}Rp, ReglistCPD8 |
Rev1+ |
Store Coprocessor Multiple Registers |
|
stcm.w CP#, {--}Rp, ReglistCPH8 |
Rev1+ |
Store Coprocessor Multiple Registers |
|
stcm.w CP#, {--}Rp, ReglistCPL8 |
Rev1+ |
Store Coprocessor Multiple Registers |
|
stcond Rp[disp], Rs |
Rev1+ |
Store Word Conditionally |
|
stdsp SP[disp], Rs |
Rev1+ |
Store Stack-Pointer Relative |
|
sthh.w Rp[disp], Rx:<part>, Ry:<part> |
Rev1+ |
Store Halfwords into Word |
|
sthh.w Rb[Ri << sa], Rx:<part>, Ry:<part> |
Rev1+ |
Store Halfwords into Word |
|
stm {--}Rp, Reglist16 |
Rev1+ |
Store Multiple Registers |
|
stmts {--}Rp, Reglist16 |
Rev1+ |
Store Multiple Registers for Task Switch |
|
stswp.h Rp[disp], Rs |
Rev1+ |
Swap and Store |
|
stswp.wRp[disp], Rs |
Rev1+ |
Swap and Store |
|
sub Rd, Rs |
Rev1+ |
Subtract (without Carry) |
|
sub Rd, Rx, Ry << sa |
Rev1+ |
Subtract (without Carry) |
|
sub Rd, imm |
Rev1+ |
Subtract (without Carry) |
|
sub Rd, imm |
Rev1+ |
Subtract (without Carry) |
|
sub Rd, Rs, imm |
Rev1+ |
Subtract (without Carry) |
|
subhh.wRd, Rx:<part>, Ry:<part> |
Rev1+ |
Subtract Halfwords into Word |
|
sub{f}{cond4} Rd, imm |
Rev2+ |
Conditional Subtract |
|
sub{cond4} Rd, Rx, Ry |
Rev2+ |
Conditional Subtract |
|
swap.b Rd |
Rev1+ |
Swap Bytes |
|
swap.bhRd |
Rev1+ |
Swap Bytes in Halfword |
|
swap.h Rd |
Rev1+ |
Swap Halfwords |
|
sync Op8 |
Rev1+ |
Synchronize memory |
|
tlbr |
Rev1+ |
Read TLB Entry |
|
tlbs |
Rev1+ |
Search TLB For Entry |
|
tlbw |
Rev1+ |
Write TLB Entry |
|
tnbz Rd |
Rev1+ |
Test if No Byte is Equal to Zero |
|
tst Rd, Rs |
Rev1+ |
Test Register |
|
xchg Rd, Rx, Ry |
Rev1+ |
Exchange Register and Memory |