Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.w Rd, Rp++ 

Rd =  *(Rp);
Rp = Rp + 4;
 
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

000

Rp

10000

Rd

3

4

5

4

2

ld.w Rd, --Rp 

Rp = Rp - 4;
Rd = *(Rp);
 
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

000

Rp

10100

Rd

3

4

5

4

3

ld.w Rd, Rp[disp] 

Rd = *(Rp + (ZE(disp5) << 2));
 
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

011

Rp

disp5

Rd

3

4

5

4

4

ld.w Rd, Rp[disp] 

Rd = *(Rp + (SE(disp16)));
 
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

111

Rp

01111

Rd

disp16

3

4

5

4

16

5

ld.w Rd, Rb[Ri<<sa] 

Rd = *(Rb + (Ri << sa2));
 
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

111

Rb

00000

Ri

0000001100

sa2

Rd

3

4

5

4

10

2

4

6

ld.w Rd, Rb[Ri:<part> << 2] 

If (part == b)
     Rd = *(Rb + (Ri[7:0] << 2) );
else if (part == l)
     Rd = *(Rb + (Ri[15:8] << 2) );
else if (part == u)
     Rd = *(Rb + (Ri[23:16] << 2) );
else
     Rd = *(Rb + (Ri[31:24] << 2) );
 
{d, b, i} ∈ {0, 1, …, 15}
part ∈ {t, u, l, b}

Rev1+

111

Rb

00000

Ri

0000111110

X

Y

Rd

3

4

5

4

10

1

1

4

Description

Format I to V: Reads the word memory location specified. Format VI: This instruction extracts a specified byte from Ri. This value is zero-extended, shifted left two positions and added to Rb to form an address. The contents of this address is loaded into Rd. The instruction is useful for indexing tables.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Note:

Format I and II: If Rd = Rp, the result is UNDEFINED.