Format |
Syntax: |
Operation: |
Operands: |
Architecture revision |
Opcode | ||||||
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1 |
pref Rp[disp] |
Prefetch cache line containing the address (Rp + SE(disp16)). |
p ∈ {0, 1, …, 15}
disp ∈ {-32768, -32767, ..., 32767} |
Rev1+ |
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This instruction allows the programmer to explicitly state that the cache should prefetch the specified line. The memory system treats this instruction in an implementation-dependent man- ner, and implementations without cache treats the instruction as a NOP. A prefetch instruction never reduces the performance of the system. If the prefetch instruction performs an action that would lower the system performance, it is treated as a NOP. For example, if the prefetch instruc- tion is about to generate an addressing exception, the instruction is cancelled and no exception is taken.
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Q: |
Not affected. |
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V: |
Not affected. |
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N: |
Not affected. |
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Z: |
Not affected. |
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C: |
Not affected. |