Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

breakpoint 

if (SR[DM]==0)
     RSR_DBG = SR;
     RAR_DBG = address of first non-completed instruction;
     SR[R] = 1;
     SR[J] = 1;
     SR[D] = 1;
     SR[M2:M0] = B'110;
     SR[DM] = 1;
     SR[EM] = 1;
     SR[GM] = 1;
     PC = EVBA+0x1C;
else
     PC = PC + 2;
 
None

Rev1+

1101011001110011

16

Description

If the on chip debug system is enabled, this instruction traps a software breakpoint for debugging. The breakpoint instruc- tion will enter debug mode disabling all interrupts and exceptions. If the on chip debug system is not enabled, this instruction will execute as a nop.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Note:

If no on chip debug system is implemented, this instruction will execute as a "NOP".