Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

satadd.hRd, Rx, Ry 

temp = ZE(Rx[15:0]) + ZE(Ry[15:0]));
if (Rx[15] AND Ry[15] AND ~temp[15]) OR (~Rx[15] AND ~Ry[15] AND temp[15]) then
      if Rx[15] == 0 then
            Rd = 0x00007fff;
      else
            Rd = 0xffff8000;
else
      Rd = SE(temp[15:0]);
 
{d, x, y} ∈ {0, 1, …, 15}

Rev1+

111

Rx

00000

Ry

000000101100

Rd

3

4

5

4

12

4

Description

Adds the two halfword registers specified and stores the result in destination register. The result is saturated if it overflows the range representable with 16 bits. If saturation occurs, the Q flag is set.

Status Flags:

Q:

Q = (Rx[15] AND Ry[15] AND ~temp[15]) OR (~Rx[15] AND ~Ry[15] AND temp[15]) OR Q

V:

V = (Rx[15] AND Ry[15] AND ~temp[15]) OR (~Rx[15] AND ~Ry[15] AND temp[15])

N:

N = Rd[15]

Z:

Z = if (Rd[15:0] == 0)

C:

C = 0