Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

sthh.w Rp[disp], Rx:<part>, Ry:<part>

*(Rp + ZE(disp8 << 2)) = {high-part, low-part};
{p, x, y} ∈ {0, 1, …, 15}
disp ∈ {0, 4, ..., 1020}
part ∈ {b,t}

Rev1+

111

Rx

11110

Ry

11

X

Y

disp8

Rp

3

4

5

4

2

1

1

8

4

2

sthh.w Rb[Ri << sa], Rx:<part>, Ry:<part>

*(Rb + (Ri << sa2)) = {high-part, low-part};
{b, i, x, y} ∈ {0, 1, …, 15}
sa  ∈ {0, 1, 2, 3}
part ∈ {b,t}

Rev1+

111

Rx

11110

Ry

10

X

Y

Ri

00

sa2

Rb

3

4

5

4

2

1

1

4

2

2

4

Description

The selected halfwords of the source registers are combined and stored to the word memory location referred to by the pointer address.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.