Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

adc Rd, Rx, Ry 

Rd = Rx + Ry + C;
 
{d, x, y} ∈ {0, 1, …, 15}

Rev1+

111

Rx

00000

Ry

000000000100

Rd

3

4

5

4

12

4

Description

Adds carry and the two registers specified and stores the result in destination register.

Status Flags:

Q:

Not affected

V:

V = (Rx[31] AND Ry[31] AND ~RES[31]) OR (~Rx[31] AND ~Ry[31] AND RES[31])

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0) AND Z

C:

C = Rx[31] AND Ry[31] OR Rx[31] AND ~RES[31] OR Ry[31] AND ~RES[31]

Example

; Add two 64-bit variables R1:R0 and R3:R2 and store the result in R1:R0 add

R0, R2

adc

R1, R1, R3