Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

st.d Rp++, Rs

*(Rp) = Rs+1:Rs;
Rp = Rp + 8;
 p ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}

Rev1+

101

Rp

10010

Rs

0

3

4

5

3

1

2

st.d --Rp, Rs

Rp = Rp - 8;
*(Rp) = Rs+1:Rs;
 p ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}

Rev1+

101

Rp

10010

Rs

1

3

4

5

3

1

3

st.d Rp, Rs

*(Rp) = Rs+1:Rs;
 p ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}

Rev1+

101

Rp

10001

Rs

1

3

4

5

3

1

4

st.d Rp[disp], Rs

*(Rp + SE(disp16)) = Rs+1:Rs;
p ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}
disp ∈ {-32768, -32767, ..., 32767}

Rev1+

111

Rp

01110

Rs

1

disp16

3

4

5

3

1

16

5

st.d Rb[Ri << sa], Rs

*(Rb + (Ri << sa2)) = Rs+1:Rs;
{b, i} ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}
sa  ∈ {0, 1, 2, 3}

Rev1+

111

Rb

00000

Ri

0000100000

sa2

Rs

3

4

5

4

10

2

4

Description

The source registers are stored to the doubleword memory location referred to by the pointer address.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Note:

For formats I. and II., if Rp == Rs the result will be UNDEFINED.