Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.uh Rd, Rp++

Rd = ZE( *(Rp) );
Rp = Rp + 2;
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

000

Rp

10010

Rd

3

4

5

4

2

ld.uh Rd, --Rp

Rp = Rp - 2;
Rd = ZE( *(Rp) );
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

000

Rp

10110

Rd

3

4

5

4

3

ld.uh Rd, Rp[disp]

Rd = ZE( *(Rp + (ZE(disp3) << 1)) );
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

100

Rp

01

disp3

Rd

3

4

2

3

4

4

ld.uh Rd, Rp[disp]

Rd = ZE( *(Rp + (SE(disp16))) );
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

111

Rp

10001

Rd

disp16

3

4

5

4

16

5

ld.uh Rd, Rb[Ri<<sa]

Rd = ZE( *(Rb + (Ri << sa2)) );
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

111

Rb

00000

Ri

0000010100

sa2

Rd

3

4

5

4

10

2

4

Description

Reads the halfword memory location specified and zero-extends it.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Note:

Format I and II: If Rd = Rp, the result is UNDEFINED.