Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

satsub.w Rd, Rx, Ry 

temp = Rx - Ry;
 
{d, x, y} ∈ {0, 1, …, 15}

Rev1+

111

Rx

00000

Ry

000000011100

Rd

3

4

5

4

12

4

2

satsub.w Rd, Rs, imm 

temp = Rs - SE(imm16));
Format I: OP1 = Rx, OP2 = Ry
Format II: OP1 = Rs, OP2 = SE(imm16)
if (OP1[31] AND ~OP2[31] AND ~temp[31]) OR (~OP1[31] AND OP2[31] AND temp[31]) then
      if(OP1[31]==0) then
            Rd =  0x7fffffff;
      else
            Rd =  0x80000000;
else
      Rd =  temp
 
{d, s} ∈ {0, 1, …, 15}
imm ∈ {-32768, -32767, ..., 32767}

Rev1+

111

Rs

01101

Rd

imm16

3

4

5

4

16

Description

Performs a subtraction and stores the result in destination register. The result is saturated if a two's complement overflow occurs. If saturation occurs, the Q flag is set.

Status Flags:

Format I: OP1 = Rx, OP2 = Ry

Format II: OP1 = Rs, OP2 = SE(imm16)

Q:

Q = (OP1[31] AND ~OP2[31] AND ~temp[31]) OR (~OP1[31] AND OP2[31] AND temp[31]) OR

Q

V:

V = (OP1[31] AND ~OP2[31] AND ~temp[31]) OR (~OP1[31] AND OP2[31] AND temp[31])

N:

N = Rd[31]

Z:

Z = (Rd[31:0] == 0)

C:

C = 0