Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

lddpc Rd, PC[disp] 

Rd = *( (PC && 0xFFFF_FFFC) + (ZE(disp7) << 2));
 
d ∈ {0, 1, …, 15}
disp ∈ {0, 4, …, 508}

Rev1+

01001

disp7

Rd

5

7

4

Description

Performs a PC relative load of a register

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.