Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

machh.d Rd, Rx:<part>, Ry:<part> 

If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]);
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
(Rd+1:Rd)[63:16] = (operand1 × operand2)[31:0] + (Rd+1:Rd)[63:16];
Rd[15:0] = 0;
 
d ∈ {0, 2, 4, …, 14}
{x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}

Rev1+

111

Rx

00000

Ry

0000010110

X

Y

Rd

3

4

5

4

10

1

1

4

Description

Multiplies the two halfword registers specified and adds the result to the specified doubleword- register. Only the 48 highest of the 64 possible bits in the doubleword accumulator are used. The 16 lowest bits are cleared. The halfword registers are selected as either the high or low part of the operand registers.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Example: 

machh.d R10, R2:t, R3:b will perform 
(R11 : R10)[63:16] = ( SE(R2[31:16])  × SE(R3[15:0])  ) + (R11 : R10)[63:16]
R10[15:0] = 0