Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

asr Rd, Rx, Ry 

Rd = ASR(Rx, Ry[4:0]);
 
d, x, y ∈ {0, 1, …, 15}

Rev1+

111

Rx

00000

Ry

000010000100

Rd

3

4

5

4

12

4

2

asr Rd, sa 

Rd = ASR(Rd, sa5); 
d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

101

Bit[4:1]

1010

Bit[0]

Rd

3

4

4

1

4

3

asr Rd, Rs, sa 

Rd = ASR(Rs, sa5);
 
{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

111

Rs

00000

Rd

00010100000

sa5

3

4

5

4

11

5

Description

Shifts all bits in a register to the right the amount of bits specified by the five least significant bits in Ry or an immediate while keeping the sign.

Status Flags:

Format I: Shamt = Ry[4:0], Op = Rx

Format II: Shamt = sa5, Op = Rd

Format III: Shamt = sa5, Op = Rs

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

if (Shamt != 0) then

C = Op[Shamt-1]

else

C = 0