Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

pushm Reglist8 

if Reglist8[0] == 1 then
     *(--SP)  =R0;
     *(--SP)  =R1;
     *(--SP)  =R2;
     *(--SP)  =R3;
if Reglist8[1] == 1 then
     *(--SP)  =R4;
     *(--SP)  =R5;
     *(--SP)  =R6;
     *(--SP)  =R7;
if Reglist8[2] == 1 then
     *(--SP)  =R8;
     *(--SP)  =R9;
if Reglist8[3] == 1 then
     *(--SP)  =R10;
if Reglist8[4] == 1 then
     *(--SP)  =R11;
if Reglist8[5] == 1 then
     *(--SP)  =R12;
if Reglist8[6] == 1 then
     *(--SP)  =LR;
if Reglist8[7] == 1 then
     *(--SP)  =PC;
 
Reglist8 ∈ {R0- R3, R4-R7, R8-R9, R10,R11, R12, LR, PC}

Rev1+

1101

Reglist8[7:1]

PC

LR

12

11

10

9-8

7-4

Reglist8[0]

3-0

0001

4

7

1

4

Description

Stores the registers specified in the instruction into consecutive words pointed to by SP.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Note:

Emtpy Reglist8 gives UNDEFINED result. The R bit in the status register has no effect on this instruction.