Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

st.h Rp++, Rs

*(Rp) = Rs[15:0];
Rp = Rp + 2;
{s , p} ∈ {0, 1, …, 15}

Rev1+

000

Rp

01011

Rs

3

4

5

4

2

st.h --Rp, Rs

Rp = Rp - 2;
*(Rp) = Rs[15:0];
{s , p} ∈ {0, 1, …, 15}

Rev1+

000

Rp

01110

Rs

3

4

5

4

3

st.h Rp[disp], Rs

*(Rp + ZE(disp3 << 1)) = Rs[15:0];
{s , p} ∈ {0, 1, …, 15}
disp ∈ {0, 2, ..., 14}

Rev1+

101

Rp

00

disp3

Rs

3

4

2

3

4

4

st.h Rp[disp], Rs

*(Rp + SE(disp16)) = Rs[15:0];
{s , p} ∈ {0, 1, …, 15}
disp ∈ {-32768, -32767, ..., 32767}

Rev1+

111

Rp

10101

Rs

disp16

3

4

5

4

16

5

st.h Rb[Ri << sa], Rs

*(Rb + (Ri << sa2)) = Rs[15:0];
{b, i, s} ∈ {0, 1, …, 15}
sa  ∈ {0, 1, 2, 3}

Rev1+

111

Rb

00000

Ri

0000101000

sa2

Rs

3

4

5

4

10

2

4

Description

The source register is stored to the halfword memory location referred to by the pointer address.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Note:

For formats I. and II., if Rp == Rs the result will be UNDEFINED.