Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

and Rd, Rs

Rd = Rd AND Rs;
{d, s} ∈ {0, 1, …, 15}

Rev1+

000

Rs

00110

Rd

3

4

5

4

2

and Rd, Rx, Ry << sa

Rd = Rx AND (Ry << sa5);
{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

111

Rx

11110

Ry

0000000

sa5

Rd

3

4

5

4

7

5

4

3

and Rd, Rx, Ry >> sa

Rd = Rx AND (Ry >> sa5);
{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

111

Rx

11110

Ry

0000001

sa5

Rd

3

4

5

4

7

5

4

Description

Performs a bitwise logical AND between the specified registers and stores the result in the desti- nation register.

Status Flags

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

Not affected