Format |
Syntax: |
Operation: |
Operands: |
Architecture revision |
Opcode | ||||||||||||||
|
1 |
and Rd, Rs |
Rd = Rd AND Rs; |
{d, s} ∈ {0, 1, …, 15} |
Rev1+ |
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2 |
and Rd, Rx, Ry << sa |
Rd = Rx AND (Ry << sa5); |
{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31} |
Rev1+ |
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|
3 |
and Rd, Rx, Ry >> sa |
Rd = Rx AND (Ry >> sa5); |
{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31} |
Rev1+ |
|
Performs a bitwise logical AND between the specified registers and stores the result in the desti- nation register.
|
Q: |
Not affected |
|
V: |
Not affected |
|
N: |
N = RES[31] |
|
Z: |
Z = (RES[31:0] == 0) |
|
C: |
Not affected |