Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

lsr Rd, Rx, Ry 

Rd = LSR(Rx, Ry[4:0]);
 
{d, x, y} ∈ {0, 1, …, 15}

Rev1+

111

Rx

00000

Ry

000010100100

Rd

3

4

5

4

12

4

2

lsr Rd, sa 

Rd = LSR(Rd, sa5);
 
d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

101

sa5[4:1]

1100

sa5[0]

Rd

3

4

4

2

0

3

lsr Rd, Rs, sa 

Rd = LSR(Rs, sa5);
 
{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

111

Rs

00000

Rd

00010110000

sa5

3

4

5

4

11

5

Description

Shifts all bits in a register the amount specified to the right. The shift amount may be specified by a register or an immediate. Zeros are shifted into the MSB.

Status Flags:

Format I: Shamt = Ry[4:0], Op = Rx

Format II: Shamt = sa5, Op = Rd

Format III: Shamt = sa5, Op = Rs

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

if Shamt != 0

C = Op[Shamt-1]

else

C = 0