Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

andh Rd, imm 

Rd[31:16] = Rd[31:16] AND imm16;
 
d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

111001

COH

00001

Rd

imm16

6

1

5

4

16

2

andh Rd, imm, COH 

Rd[31:16] = Rd[31:16] AND imm16;
Rd[15:0] = 0;
 
d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

111001

COH

00001

Rd

imm16

6

1

5

4

16

3

andl Rd, imm 

Rd[15:0] = Rd[15:0]   AND imm16;
 
d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

111000

COH

00001

Rd

imm16

6

1

5

4

16

4

andl Rd, imm, COH 

Rd[15:0] = Rd[15:0]   AND imm16;
Rd[31:16] = 0;
 
d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

111000

COH

00001

Rd

imm16

6

1

5

4

16

Description

Performs a bitwise logical AND between the high or the low halfword in the specified register and a constant. The result is stored in the high or the low halfword of the destination register while the other bits remain unchanged. The Clear Other Half (COH) parameter allows the other half to be cleared.

Status Flags:

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

Not affected