Format |
Syntax: |
Operation: |
Operands: |
Architecture revision |
Opcode | ||||||||||||
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1 |
ldm Rp{++}, Reglist16 |
Loadaddress = Rp;
if Reglist16[PC] == 1 then
if Rp == PC then
Loadaddress = SP;
PC = *(Loadaddress++);
if Rp == PC then
if Reglist16[LR,R12] == B'00
R12 = 0;
else if Reglist16[LR,R12] == B'01
R12 = 1;
else
R12 = - 1;
Test R12 and update flags;
else
if Reglist16[LR] == 1
LR = *(Loadaddress++);
if Reglist16[SP] == 1
SP = *(Loadaddress++);
if Reglist16[R12] == 1
R12 = *(Loadaddress++);
Test R12 and update flags;
else
if Reglist16[LR] == 1
LR = *(Loadaddress++);
if Reglist16[SP] == 1
SP = *(Loadaddress++);
if Reglist16[R12] == 1
R12 = *(Loadaddress++);
for (i = 11 to 0)
if Reglist16[i] == 1 then
Ri =
*(Loadaddress++);
if Opcode[++] == 1 then
if Rp == PC then
SP = Loadaddress;
else
Rp = Loadaddress; |
Reglist16 ∈ {R0, R1, R2, ..., R12, LR, SP, PC}
p ∈ {0, 1, …, 15} |
Rev1+ |
|
Loads the consecutive words pointed to by Rp into the registers specified in the instruction. The PC can be loaded, resulting in a jump to the loaded target address. If PC is loaded, the return value in R12 is tested and the flags are updated. The return value may optionally be set to -1, 0 or 1.
|
Flags are only updated if Reglist16[PC] == 1. |
|
|
They are set as the result of the operation cp R12, 0. |
|
|
Q: |
Not affected |
|
V: |
V = 0 |
|
N: |
N = RES[31] |
|
Z: |
Z = (RES[31:0] == 0) |
|
C: |
C = 0 |
Emtpy Reglist16 gives UNDEFINED result. If Rp is in Reglist16 and pointer is written back the result is UNDEFINED. The R bit in the status register has no effect on this instruction.