Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

lsl Rd, Rx, Ry 

Rd = LSL(Rx, Ry[4:0]);
 
{d, x, y} ∈ {0, 1, …, 15}

Rev1+

111

Rx

00000

Ry

000010010100

Rd

3

4

5

4

12

4

2

lsl Rd, sa 

Rd = LSL(Rd, sa5);
 
d ∈ {0, 1, …, 15}
sa  ∈ {0, 1, …, 31}

Rev1+

101

sa5[4:1]

1011

sa5[0]

Rd

3

4

4

1

4

3

lsl Rd, Rs, sa 

Rd = LSL(Rs, sa5);
 
{d,s} ∈ {0, 1, …, 15}
sa  ∈ {0, 1, …, 31}

Rev1+

111

Rs

00000

Rd

00010101000

sa5

3

4

5

4

11

5

Description

Shifts all bits in a register the amount of bits specified to the left. The shift amount can reside in a register or be specified as an immediate. Zeros are shifted into the LSBs. The last bit that is shifted out is placed in C.

Status Flags:

Format I: Shamt = Ry[4:0], Op = Rx

Format II: Shamt = sa5, Op = Rd

Format III: Shamt = sa5, Op = Rs

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

if Shamt != 0

C = Op[32-Shamt]

else

C = 0