Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

macwh.d Rd, Rx, Ry:<part> 

operand1 = Rx;
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
(Rd+1:Rd)[63:16] = (operand1 × operand2)[47:0] + (Rd+1:Rd)[63:16];
Rd[15:0] = 0;
 
d ∈ {0, 2, …, 14}
{x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}

Rev1+

111

Rx

00000

Ry

00001100100

Y

Rd

3

4

5

4

11

1

4

Description

Multiplies the word and halfword register specified and adds the result to the specified double- word-register. The halfword register is selected as either the high or low part of Ry. Only the 48 highest of the 64 possible bits in the doubleword accumulator are used. The 16 lowest bits are cleared.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Example: 

macwh.dR10, R2, R3:bwill perform 
(R11:R10)[63:16] = (R2 × SE(R3[15:0])) + (R11:R10)[63:16]
R10[15:0]  = 0