Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

divs Rd, Rx, Ry 

Rd = Rx / Ry;
Rd+1 = Rx % Ry;
 
d ∈ {0, 2, …, 14}
{x, y} ∈ {0, 1, …, 15}

Rev1+

111

Rx

00000

Ry

000011000000

Rd

3

4

5

4

12

4

Description

Performs a signed divide between the two 32-bit register specified. The quotient is returned in Rd, the remainder in Rd+1. No exceptions are taken if dividing by 0. Result in Rd and Rd+1 is UNDEFINED when dividing by 0. The sign of the remainder will be the same as the dividend, and the quotient will be negative if the signs of Rx and Ry are opposite.

Status Flags

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected