Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

addhh.wRd, Rx:<part>, Ry:<part> 

If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]);
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
Rd = operand1 + operand2;
 
{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}

Rev1+

111

Rx

00000

Ry

0000111000

X

Y

Rd

3

4

5

4

10

1

2

0

Description

Adds the two halfword registers specified and stores the result in the destination word-register. The halfword registers are selected as either the high or low part of the operand registers.

Status Flags:

OP1 = operand1, OP2 = operand2

Q:

Not affected

V:

V = (OP1[31] AND OP2[31] AND ~RES[31]) OR (~OP1[31] AND ~OP2[31] AND RES[31])

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = OP1[31] AND OP2[31] OR OP1[31] AND ~RES[31] OR OP2[31] AND ~RES[31]

Example: 

addhh.wR10, R2:t, R3:b
will perform R10 = SE(R2[31:16])  + SE(R3[15:0])