Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

popm Reglist8 {, R12 = {-1, 0, 1}} 

if Reglist8[PC] AND k == B'1
     PC   = *(SP++)
     if Reglist8[LR:R12] == B'00
           R12   =   0;
     else if Reglist8[LR:R12] == B'01
           R12   =   1;
     else
           R12   =    - 1;
     Test R12 and update flags;
else 
     if Reglist8[PC] == 1 then
           PC   = *(SP++);
     if Reglist8[LR] == 1 then
           LR   = *(SP++);
     if Reglist8[R12] == 1 then
           R12   =*(SP++);
     if Reglist8[PC] == 1 then
           Test R12 and update flags;
if Reglist8[5] == 1 then
     R11   =*(SP++);
if Reglist8[4] == 1 then
     R10   =*(SP++);
if Reglist8[3] == 1 then
     R9   = *(SP++);
     R8   = *(SP++);
if Reglist8[2] == 1 then
     R7   = *(SP++);
     R6   = *(SP++);
     R5   = *(SP++);
     R4   = *(SP++);
if Reglist8[1] == 1 then
     R3   = *(SP++);
     R2   = *(SP++);
     R1   = *(SP++);
     R0   = *(SP++);
 
Reglist8 ∈ {R0- R3, R4-R7, R8-R9, R10,R11, R12, LR, PC}

Rev1+

1101

Reglist8

PC

LR

12

11

10

9-8

7-4

3-0

k

010

4

8

1

3

Description

Loads the consecutive words pointed to by SP into the registers specified in the instruction. The PC can be loaded, resulting in a jump to the loaded value. If PC is popped, the return value in R12 is tested and the flags are updated. R12 can optionally be updated with -1, 0 or 1. The k bit in the instruction coding is used to optionally let the POPM instruction update the return register R12 with the values -1, 0 or 1.

Status Flags:

Flags are only updated if Reglist8[PC] == 1.

They are set as the result of the operation cp R12, 0

Q:

Not affected

V:

V = 0

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = 0

Note:

Emtpy Reglist8 gives UNDEFINED result. The R bit in the status register has no effect on this instruction.