Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.sh Rd, Rp++

Rd = SE( *(Rp) );
Rp = Rp + 2;
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

000

Rp

10001

Rd

3

4

5

4

2

ld.sh Rd, --Rp

Rp = Rp - 2;
Rd = SE( *(Rp) );
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

000

Rp

10101

Rd

3

4

5

4

3

ld.sh Rd, Rp[disp]

Rd = SE( *(Rp + (ZE(disp3) << 1)) );
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

100

Rp

00

disp3

Rd

3

4

2

3

4

4

ld.sh Rd, Rp[disp]

Rd = SE( *(Rp + (SE(disp16)));
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

111

Rp

10000

Rd

disp16

3

4

5

4

16

5

ld.sh Rd, Rb[Ri<<sa]

Rd = SE( *(Rb + (Ri << sa2));
d, p, b, i ∈ {0, 1, …, 15}

Rev1+

111

Rb

00000

Ri

0000010000

sa2

Rd

3

4

5

4

10

2

4

Description

Reads the halfword memory location specified and sign-extends it.

Status Flags:

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Note:

Format I and II: If Rd = Rp, the result is UNDEFINED.