Encoding:

001000

00001

001

1010110

000

Format:

DMT rt

MIPS MT

Disable Multi-Threaded Execution

Purpose:

Disable Multi-Threaded Execution

To return the previous value of the VPEControl register (see Section 6.5) and disable multi-threaded execution. If

DMT is specified without an argument, GPR r0 is implied, which discards the previous value of the VPEControl register.

Description:

GPR[rt] = VPEControl; VPEControl_TE = 0

The current value of the VPEControl register is loaded into general register rt. The Threads Enable (TE) bit in the

VPEControl register is then cleared, suspending concurrent execution of instruction streams other than that which

issues the DMT. This is independent of any per-TC halted state.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation:

This operation specification is for the general multi-threading enable/disable operation, with the sc (set/clear) field as a variable. The individual instructions EMT and DMT have a specific value for the sc field.

if IsCoprocessorEnabled(0) then
   if Config3_MT then
      data = VPEControl
      GPR[rt] = data
      VPEControl_TE = sc
   else
      SignalException(ReservedInstruction)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Implementation Notes:

DMT accesses a COP0 register and assumes a hard-coded value of rd=1 and sel=1 for VPEControl.

The sc field indicates whether the operation is a bit clear or set, as follows:

Operation

Clear bit specified by the pos field

Set bit specified by the pos field

Instruction exception checks excluded for clarity) is:

data = CPR[0,rd, sel]
GPR[rt] = data
CPR[0, rd, sel]_pos = sc

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading VPEControl into a GPR, clearing the TE bit to create a temporary value in a second GPR, and writing that value back to VPEControl. Unlike the multiple instruction sequence, however, the DMT instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception.

The effect of a DMT instruction may not be instantaneous. An instruction hazard barrier, e.g., JR.HB, is required to guarantee that all other threads have been suspended. If a DMT instruction is followed in the same instruction stream by an MFC0 or MFTR from the VPEControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the DMT and the read of VPEControl to guarantee that the new state of TE will be accessed by the read.

Encoding:

001000

00000

001

1010110

000

Format:

DVPE rt

MIPS MT

Disable Virtual Processor Execution

Purpose:

Disable Virtual Processor Execution

To return the previous value of the MVPControl register (see Section 6.2) and disable multi-VPE execution. If DVPE is specified without an argument, GPR r0 is implied, which discards the previous value of the MVPControl register.

Description:

GPR[rt] = MVPControl; MVPControl_EVP = 0

The current value of the MVPControl register is loaded into general register rt. The Enable Virtual Processors (EVP) bit in the MVPControl register is then cleared, suspending concurrent execution of instruction streams other than the instruction stream that issues the DVPE.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation:

This operation specification is for the general VPE enable/disable operation, with the sc (set/clear) field as a variable.

The individual instructions EVPE and DVPE have a specific value for the sc field.

if IsCoprocessorEnabled(0) then
   if Config3_MT then
      data = MVPControl
      GPR[rt] = data
      if(VPEConf0_MVP = 1) then
         MVPControl_EVP = sc
      endif
   else
      SignalException(ReservedInstruction)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Implementation Notes:

DVPE accesses a COP0 register and assumes a hard-coded value of rd=0 and sel=1 for MVPControl.

The sc field indicates whether the operation is a bit clear or set, as follows:

scOperation

0Clear bit specified by the pos field

1Set bit specified by the pos field

The general description of the final operation provided by this operation (with Coprocessor Unusable and Reserved

Instruction exception checks excluded for clarity) is:

data = CPR[0,rd, sel]
GPR[rt] = data
CPR[0, rd, sel]_pos = sc

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading MVPControl into a GPR, clearing the EVP bit to create a temporary value in a second GPR, and writing that value back to MVPControl. Unlike the multiple instruction sequence, however, the DVPE instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception, nor by the scheduling of a different instruction stream.

The effect of a DVPE instruction may not be instantaneous. An instruction hazard barrier, e.g., JR.HB, is required to guarantee that all other TCs have been suspended.

If a DVPE instruction is followed in the same instruction stream by an MFC0 or MFTR from the MVPControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the DVPE and the read of MVPControl to guarantee that the new state of EVP will be accessed by the read.

Encoding:

001000

00001

001

1010110

000

Format:

EMT rt

MIPS MT

Enable Multi-Threaded Execution

Purpose:

Enable Multi-Threaded Execution

To return the previous value of the VPEControl register (see Section 6.5) and to enable multi-threaded execution. If

EMT is specified without an argument, GPR r0 is implied, which discards the previous value of the VPEControl register.

Description:

GPR[rt] = VPEControl; VPEControl_TE = 1

The current value of the VPEControl register is loaded into general register rt. The Threads Enable (TE) bit in the

VPEControl register is then set, allowing multiple instruction streams to execute concurrently.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   if Config3_MT then
      data = VPEControl
      GPR[rt] = data
      VPEControl_TE = sc
   else
      SignalException(ReservedInstruction)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Implementation Notes:

EMT accesses a COP0 register and assumes a hard-coded value of rd=1 and sel=1 for VPEControl.

The sc field indicates whether the operation is a bit clear or set, as follows:

scOperation

Clear bit specified by the pos field

Set bit specified by the pos field

The general description of the final operation provided by this operation (with Coprocessor Unusable and Reserved

Instruction exception checks excluded for clarity) is:

data = CPR[0,rd, sel]
GPR[rt] = data
CPR[0, rd, sel]_pos = sc

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading VPEControl into a GPR, setting the TE bit to create a temporary value in a second GPR, and writing that value back to VPEControl. Unlike the multiple instruction sequence, however, the EMT instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception.

If an EMT instruction is followed in the same instruction stream by an MFC0 or MFTR from the VPEControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the EMT and the read of VPEControl to guarantee that the new state of TE will be accessed by the read.

Encoding:

001000

00000

001

1010110

000

Format:

EVPE rt

MIPS MT

Enable Virtual Processor Execution

Purpose:

Enable Virtual Processor Execution

To return the previous value of the MVPControl register (see Section 6.2) and enable multi-VPE execution. If EVPE is specified without an argument, GPR r0 is implied, which discards the previous value of the MVPControl register.

Description:

GPR[rt] = MVPControl; MVPControl_EVP = 1

The current value of the MVPControl register is loaded into general register rt. The Enable Virtual Processors (EVP) bit in the MVPControl register is then set, enabling concurrent execution of instruction streams on all non-inhibited

Virtual Processing Elements (VPEs) on a processor.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation:

This operation specification is for the general VPE enable/disable operation, with the sc (set/clear) field as a variable.

The individual instructions EVPE and DVPE have a specific value for the sc field.

if IsCoprocessorEnabled(0) then
   if Config3_MT then
      data = MVPControl
      GPR[rt] = data
      if(VPEConf0_MVP = 1) then
         MVPControl_EVP = sc
      endif
   else
      SignalException(ReservedInstruction)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Implementation Notes:

EVPE accesses a COP0 register and assumes a hard-coded value of rd=0 and sel=1 for MVPControl.

The sc field indicates whether the operation is a bit clear or set, as follows:

scOperation

Clear bit specified by the pos field

Set bit specified by the pos field

The general description of the final operation provided by this operation (with Coprocessor Unusable and Reserved

Instruction exception checks excluded for clarity) is:

data = CPR[0,rd, sel]
GPR[rt] = data
CPR[0, rd, sel]_pos = sc

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading MVPControl into a GPR, setting the EVP bit to create a temporary value in a second GPR, and writing that value back to MVPControl. Unlike the multiple instruction sequence, however, the EVPE instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception, nor by the scheduling of a different instruction stream.

If an EVPE instruction is followed in the same instruction stream by an MFC0 or MFTR from the MVPControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the EVPE and the read of MVPControl to guarantee that the new state of EVP will be accessed by the read.

Encoding:

001000	rt	rs	rd	x	1000101	000
6	5	5	5	1	7	3

Format:

FORK rd, rs, rt

MIPS MT

Allocate and Schedule a New Thread

Purpose:

Allocate and Schedule a New Thread

To cause a thread context to be allocated and associated with a new instruction stream.

Description: NewThread's GPR[rd] = GPR[rt], NewThread's TCRestart = GPR[rs]

The FORK instruction causes a free dynamically allocatable thread context (TC) to be allocated and activated on the issuing VPE. It takes two operand values from GPRs. The rs value is used as the starting fetch address and execution mode for the new thread. The rt value is copied into GPR rd of the new TC. The TCStatus register of the new TC is set up as a function of the FORKing TC as described in Section 6.12. If the UserLocal register is implemented, the

UserLocal value of the FORKing TC is also copied to the new TC. The newly allocated TC will begin executing

instructions according to the implemented scheduling policy if and when multi-threaded execution is otherwise enabled.

Restrictions:

If no free, non-halted, dynamically allocatable TC is available for the fork, a Thread Exception is raised for the FORK instruction, with the VPEControl.EXCPT CP0 register field set to 1 to indicate the Thread Overflow case.

Processors which implement only a single TC per VPE may implement FORK by simply raising the Thread Exception and indicating the Overflow.

Any exceptions associated with the virtual address passed in rs will be taken by the new thread of execution.

Operation:

if Config3_MT = 1 then
   success = 0
   for t in 0...MVPConf0_PTC
      if TC[t].TCBind_CurVPE = TCBind_CurVPE then
         if (TC[t].TCStatus_DA = 1)
             and (TC[t].TCHalt^H = 0)
             and (TC[t].TCStatus_A = 0)
             and (success = 0) then
                TC[t].TCRestart = GPR[rs]
                TC[t].GPR[rd] = GPR[rt]
                if (Config3_ULRI = 1) then
                   TC[t].UserLocal = UserLocal
                endif
                activated = 1 
                priorcu = TC[t].TCStatus_TCU3..TCU0
                priormx = TC[t].TCStatus_TMX
                priorixmt = TC[t].TCStatus_IXMT
                TC[t].TCStatus = priorcu || priormx || Status_FR|| 0⁵|| 1 || 
ImpDep⁴
                              || 1 || 0 || activated|| Status_KSU|| priorixmt
                              || 0² || TCStatus_TASID
                success = 1
         endif
      endif
   endfor
   if success = 0
      VPEControl_EXCPT = 1
   endif
else
   SignalException(ReservedInstruction)
endif

Exceptions:

Reserved Instruction

Thread

Encoding:

001000	rt	rs	sel	u	100011	h	000
6	5	5	5	1	6	1	3

Format:

MFTR rt, rs, u, sel, h

MIPS MT

Move from Thread Context

Purpose:

Move from Thread Context

To move the contents of a register within a targeted thread context or VPE into a general register of the current thread.

Description:

GPR[rt] = TC[VPEControl_TargTC][u,rs,sel,h]

The contents of the register specified are loaded into general register rt. The target context to be read is determined by the value of the TargTC field of the CP0 VPEControl register (see Section 6.5). The register to be read within the selected context is determined by the value in the rs operand register, in conjunction with the u and sel bits of the

MFTR instruction, according to table Table 5.1. If the register to be read is instantiated per-processor or per-VPE, rather than per-TC, the register selected is that of the processor within which the target TC is instantiated, or the VPE to which the target TC is bound (see Section 6.13), respectively.

Coprocessor 1 and 2 registers and DSP accumulators referenced by the MFTR instruction are those bound to the target TC. The TCUx bits and TMX bit of the target TC’s TCStatus register are ignored.

If the selected register is not implemented on the processor, or otherwise not accessible to the TC that issued the

MFTR, as in the case of references to TCs and coprocessor resources bound to other VPEs when the VPE executing the MFTR does not have MVP set in VPConfig0, the resulting rt value is -1.

Release 5 adds the instruction MFTHC0.

The Idiom(s) column in Table 5.1 specifies the assembler idiom that is used to express an access to the particular register.

The selected value is written into the target register rt. If the precision of the source register is less than the precision of the target GPR, the value is sign-extended.

The h bit of the instruction word selects the high-order half of the source register in instances where the source is a register of greater precision than the target GPR.

Restrictions:

An MFTR instruction where the target TC is not in a Halted state (i.e., TCHalt.H is not set), or where a TC other than the one issuing the MFTR is active in the target VPE on a reference to a per-VPE CP0 register, may result in an

If the target TC is blocked but not halted, then the thread issuing the MFTR instruction may be blocked indefinitely.

This is due to the target TC waiting on an external event that may never happen. It is recommended that the

TCStatus_RNST bit of the target TC be checked before issuing the MFTR instruction.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In any implementation with Floating-Point-Unit, if TCStatus_TFR is set so the effective FPR width matches the GPR width, a MFTR instruction targetting one of the FPRs with h=1 will cause UNPREDICTABLE results.

Operation:

if IsCoprocessorEnabled(0) then
   if VPEConf0_MVP = 0 and ( TC[VPEControl_TargTC].TCBind_CurVPE != TCBind_CurVPE) then
      data = -1
   else if VPEControl_TargTC > MVPConf0_PTC then
      data = -1
   else if u = 0 then
      data = TC[VPEControl_TargTC].CPR[0,rs,sel]
   else
      if h = 1 then
         topbit = 63
         bottombit = 32
      else
         topbit = 31
         bottombit = 0
      endif
      case sel
         0: data = TC[VPEControl_TargTC].GPR[rs]_{topbit..bottombit}
         1: case rs
             0: data = TC[VPEControl_TargTC].Lo
             1: data = TC[VPEControl_TargTC].Hi
             2: data = TC[VPEControl_TargTC].ACX
             4: data = TC[VPEControl_TargTC].DSPLo[1]
             5: data = TC[VPEControl_TargTC].DSPHi[1]
             6: data = TC[VPEControl_TargTC].DSPACX[1]
             8: data = TC[VPEControl_TargTC].DSPLo[2]
             9: data = TC[VPEControl_TargTC].DSPHI[2]
             10:data = TC[VPEControl_TargTC].DSPACX[2]
             12 data = TC[VPEControl_TargTC].DSPLo[3]
             13:data = TC[VPEControl_TargTC].DSPHi[3]
             14:data = TC[VPEControl_TargTC].DSPACX[3]
             16:data = TC[VPEControl_TargTC].DSPControl
             otherwise: data = UNPREDICTABLE
             2: if ( ( Config_AT = 0 and Status_FR = 0) or 
                     ( Config_AT = 1 or Config_AT = 2) )
                   // GPR and FPR widths match
                   if (h = 0 ) 
                       data = TC[VPEControl_TargTC].FPR[rs]
                   else
                       UNPREDICTABLE
                   endif
                elseif (Config_AT = 0 and Status_FR = 1)
                    // 32-bit GPRs and 64-bit FPRs
                    data = TC[VPEControl_TargTC].FPR[rs]_{topbit..bottombit}
                endif
         3: data = TC[VPEControl_TargTC].FPCR[rs]
         4: data = TC[VPEControl_TargTC].CP2CPR[rx||rs]_{topbit..bottombit}
         5: data = TC[VPEControl_TargTC].CP2CCR[rx||rs]_{topbit..bottombit}
         otherwise: data = UNPREDICTABLE
   if h = 1 then
      data = data_63..32
   endif
   GPR[rt] = data_31..0
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

001000	rt	rs	sel	u	100111	h	000
6	5	5	5	1	6	1	3

Format:

MTTR rt, rs, u, sel, h

MIPS MT

Move to Thread Context

Purpose:

Move to Thread Context

To move the contents of a general register of the current thread into a register within a targeted thread context.

Description:

TC[VPEControl_TargTC][u,rs,sel,h] = GPR[rt]

The contents of the rt register specified are written into a register of an arbitrary thread context (TC) or virtual processor (VPE).

The target context to be written is determined by the value of the TargTC field of the CP0 VPEControl register (see

Section 6.5). The register to be written within the selected context is determined by the value in the rs operand register, in conjunction with the u and sel bits of the MTTR instruction, according to Table 5.2. If the register to be written is instantiated per-processor or per-VPE, rather than per-TC, the register selected is that of the processor within which the target TC is instantiated, or the VPE to which the target TC is bound (see “6.13 TCBind Register

(CP0 Register 2, Select 2)” on page 81), respectively.

Coprocessor 1 and 2 registers and DSP accumulators referenced by the MTTR instruction are those bound to the target TC. The TCUx bits and TMX bit of the target TC’s TCStatus register are ignored.

If the selected register is not implemented on the processor, or otherwise not accessible to the TC issuing the MTTR, as in the case of references to TCs and coprocessor resources bound to other VPEs when the VPE executing the

MTTR does not have MVP set in VPConfig0, MTTR has no effect.

Release 5 adds the MTTHC0 instruction.

The Idiom(s) column in Table 5.2 specifies the assembler idiom that is used to express an access to the particular register.

Restrictions:

The effect on a TC that is not in a Halted state (i.e., TCHalt.H is 0) of an MTTR instruction targeting that TC may be transient and unstable, but MTTRs setting a TCHalt H bit are always effective until overridden by another MTTR.

Processor state following an MTTR instruction modifying a per-VPE CP0 register is UNPREDICTABLE if a TC other than the one issuing the MTTR is concurrently active on the targeted VPE.

This is due to the target TC waiting on an external event that may never happen. It is recommended that the

TCStatus_RNST bit of the target TC be checked before issuing the MTTR instruction.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

If the target register is a Floating-Point Control register, hardware must not generate a Floating-Point Exception due to any value written into Floating Point Exception Cause Field by the MTTR instruction.

In any implementation with Floating-Point-Unit, if TCStatus_TFR is set so the effective FPR width matches the GPR width, a MFTR instruction targeting one of the FPRs with h=1 will cause UNPREDICTABLE results.

Operation:

if IsCoprocessorEnabled(0) then
   if VPEConf0_MVP = 0 and ( TC[VPEControl_TargTC].TCBind_CurVPE != TCBind_CurVPE) then
      NOOP
   else if VPEControl_TargTC > MVPConf0_PTC then
      NOOP
   else
      if h = 1 then
         topbit = 63
         bottombit = 32
      else
         topbit = 31
         bottombit = 0
      endif
      if u = 0 then
         TC[VPEControl_TargTC].CPR[0,rs,sel]_{topbit..bottombit} = GPR[rt]
      else
         case sel
             0: TC[VPEControl_TargTC].GPR[rs] = GPR[rt]_{topbit..bottombit}
             1: case rs
                0: TC[VPEControl_TargTC].Lo = GPR[rt]
                1: TC[VPEControl_TargTC].Hi = GPR[rt]
                2: TC[VPEControl_TargTC].ACX = GPR[rt]
                4: TC[VPEControl_TargTC].DSPLo[1] = GPR[rt]
                5: TC[VPEControl_TargTC].DSPHi[1] = GPR[rt]
                6: TC[VPEControl_TargTC].DSPACX[1] = GPR[rt]
                8: TC[VPEControl_TargTC].DSPLo[2] = GPR[rt]
                9: TC[VPEControl_TargTC].DSPHi[2] = GPR[rt]
                10:TC[VPEControl_TargTC].DSPACX[2] = GPR[rt]
                12:TC[VPEControl_TargTC].DSPLo[3] = GPR[rt]
                13:TC[VPEControl_TargTC].DSPHi[3] = GPR[rt]
                14:TC[VPEControl_TargTC].DSPACX[3] = GPR[rt]
                16:TC[VPEControl_TargTC].DSPControl = GPR[rt]
                otherwise: UNPREDICTABLE
             2: if ( ( Config_AT = 0 and Status_FR = 0) or 
                     ( Config_AT = 1 or Config_AT = 2) )
                   // GPR and FPR widths match
                   if (h = 0) 
                       TC[VPEControl_TargTC].FPR[rs] = GPR[rt]
                   else
                       UNPREDICTABLE
                   endif
                elseif (Config_AT = 0 and Status_FR = 1)
                    // 32-bit GPRs and 64-bit FPRs
                    TC[VPEControl_TargTC].FPR[rs]_{topbit..bottombit} = GPR[rt]
                endif
             3: TC[VPEControl_TargTC].FPCR[rs] = GPR[rt]
             5: TC[VPEControl_TargTC].CP2CCR[rx||rs]_{topbit..bottombit} = GPR[rt]
             otherwise: UNPREDICTABLE
      endif
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

001000	rt	rs	x	1001101	000
6	5	5	6	7	3

Format:

YIELD rt, rs

MIPS MT

Conditionally Deschedule or Deallocate the Current Thread

Purpose:

Conditionally Deschedule or Deallocate the Current Thread

To suspend the current thread of execution, and conditionally deallocate the associated thread context.

Description:

The YIELD instruction takes a single input operand value from a GPR rs. This value is a descriptor of the circumstances under which the issuing thread should be rescheduled.

If GPR rs is zero, the thread is not to be rescheduled at all, and it is instead deallocated and its associated TC storage freed for allocation by a subsequent FORK issued by some other thread.

If GPR rs is negative one (-1), the thread remains eligible for scheduling at the next opportunity, but invokes the processor’s scheduling logic and relinquishes the CPU for any other threads which ought to execute first according to the implemented scheduling policy.

If GPR rs is negative two (-2), the processor’s scheduling logic is not invoked, and the only effect of the instruction is to retrieve the rt value (see below).

All other negative values of the rs register are reserved for future architectural definition by MIPS.

Positive values of rs are treated as a vector of YIELD qualifier (YQ) bits which describe an implementation-dependent set of external or internal core signal conditions under which the YIELDing thread is to be rescheduled. Up to 31 bits of YIELD qualifier state may be supported by a processor, but implementations may provide fewer. To be usable, a YIELD qualifier bit must be enabled in the YQMask register (see Section 6.8).

If no set bit of rs matches with a set, enabled YQ bit, the TC is blocked until one or more active bits of enabled YQ input match corresponding rs bits. If and when one or more bits match, the TC resumes a running state, and may be rescheduled for execution in accordance with the thread scheduling policy in effect.

The rt output operand specifies a GPR which is to receive a result value. This result contains the bit vector of YQ inputs values enabled by the YQMask register at the time the YIELD completes. Thus, any YQ state that can be waited upon by a YIELD with a positive rs value can also be polled via a YIELD with an rs value of -1 or -2. The value of any rt bits that do not correspond to set bits in the YQMask register is implementation-dependent, typically 0. A zero value of the rt operand field, selecting GPR 0, indicates that no result value is desired.

Implementation Notes:

The writeback of the destination register should be scheduled only when it is known that the YIELD is not blocked.

Accesses to the register via MTTR or MFTR targeting a TC blocked on a YIELD should not be blocked by a dependency on the YIELD completion.

Restrictions:

Bits 15:10 must be set to 0 by software. Hardware must ignore these bits.

If a positive rs value includes a set bit that is not also set in the YQMask register, a Thread exception is raised for the

YIELD instruction, with the EXCPT field of the VPEControl register set to 2 to indicate the Invalid Qualifier case.

If no non-halted dynamically allocatable TC would be activated after a YIELD whose rs value is 0, a Thread exception is raised for the YIELD instruction, with the EXCPT field of the VPEControl register set to 0 to indicate the

Thread Underflow case.

If the processor’s scheduling logic would be invoked as a consequence of an otherwise unexceptional YIELD, one

YSI bit of VPEControl and the DT bit of TCStatus are set, a Thread exception is raised for the YIELD instruction, with

the VPEControl EXCPT field set to 4 to indicate the YIELD Scheduler case.

If multi-threaded operation is unsupported, a Reserved Instruction Exception is raised for the YIELD instruction.

Processor behavior is UNPREDICTABLE if a YIELD instruction is placed in a branch or jump delay slot.

Operation:

if Config3_MT = 1 then
   if GPR[rs] = 0 then
      ok = 0
      for t in 0...MVPConf0_PTC 
         if (TC[t].TCBind_CurVPE = TCBind_CurVPE )
          and (TC[t].TCBind_CurTC != TCBind_CurTC )
          and (TC[t].TCStatus_DA = 1)
          and (TC[t].TCHalt_H = 0)
          and (TC[t].TCStatus_A = 1) then
             ok = 1
         endif
      endfor
      if ((ok = 1) and not ((VPEControl_YSI = 1) and (TCStatus_DT = 1))) then
          TCStatusA = 0
      else
          VPEControl_EXCPT = 0
         SignalException(Thread)
      endif
   else if GPR[rs] > 0 then
      if (GPR[rs] and (not YQMask)) != 0 then
         VPEControl_EXCPT = 2
         SignalException(Thread)
      else
         SetThreadRescheduleCondition(GPR[rs] and YQMask)
      endif
   endif
   if GPR[rs] != -2 then
      if (VPEControl_YSI = 1) and (TCStatus_DT = 1) then
         VPEControl_EXCPT = 4
         SignalException(Thread)
      else
         ScheduleOtherThreads()
      endif
   endif
   if rt != 0 then
      GPR[rt] = GetThreadRescheduleCondition()
   endif
else
   SignalException(ReservedInstruction)
endif

Exceptions:

Reserved Instruction

Thread