Assembly:

ADD rd, rs, rt

Purpose:

Add. Add two 32-bit signed integers in registers $rs and $rt, placing the 32-bit result inregister $rd, and trapping on overflow.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
sum = GPR[rs] + GPR[rt]
if overflows(sum, nbits=32):
    raise exception('OV')
GPR[rd] = sign_extend(sum, from_nbits=32)

Exceptions:

Overflow.

Assembly:

ADDIU rt, rs, imm

Purpose:

Add Immediate (Untrapped). Add immediate value imm to the 32-bit integer value in register$rs, placing the 32-bit result in register $rt, and not trapping on overflow.

Availability:

nanoMIPS, availability varies by format.

Format:

ADDIU[32]

imm = u

ADDIU[48], not available in NMS

if C0.Config5.NMS == 1:
    raise exception('RI')
imm = sign_extend(s, from_nbits=32)
rs = rt

ADDIU[GP48], not available in NMS, not available in P64 mode

if C0.Config5.NMS == 1:
    raise exception('RI')
if pointers_are_64_bits():
    raise behaves_like('DADDIU[GP48]')
imm = sign_extend(s, from_nbits=32)
rs = 28

ADDIU[GP.B], not available in P64 mode

if pointers_are_64_bits():
    raise behaves_like('DADDIU[GP.B]')
imm = u
rs = 28

ADDIU[GP.W], not available in P64 mode

if pointers_are_64_bits():
    raise behaves_like('DADDIU[GP.W]')
imm = u
rs = 28

ADDIU[R1.SP], not available in P64 mode

if pointers_are_64_bits():
    raise behaves_like('DADDIU[R1.SP]')
rt = decode_gpr(rt3, 'gpr3')
rs = 29
imm = u

ADDIU[R2]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
imm = u

ADDIU[RS5]

rs = rt
imm = sign_extend(s, from_nbits=4)

ADDIU[RS5] with rt=0 is used to provide a 16 bit NOP instruction.

ADDIU[NEG]

imm = -u

Operation:

sum = GPR[rs] + imm
GPR[rt] = sign_extend(sum, from_nbits=32)

Exceptions:

Reserved Instruction for ADDIU[48] and ADDIU[GP48] formats on NMS cores.

Assembly:

ADDIUPC rt, imm

Purpose:

Add Immediate (Untrapped) to PC. Compute address by adding immediate value imm to thePC and placing the result in register $rt, not trapping on overflow.

Availability:

nanoMIPS, availability varies by format.

Format:

ADDIUPC[32], not available in P64 mode

if pointers_are_64_bits():
    raise behaves_like('DADDIUPC[32]')
s = sign_extend(s[21] @ s[20:1] @ '0')
imm = s + 4

ADDIUPC[48], not available in NMS, not available in P64 mode

if C0.Config5.NMS == 1:
    raise exception('RI')
if pointers_are_64_bits():
    raise behaves_like('DADDIUPC[48]')
s = sign_extend(s[31:16] @ s[15:0])
imm = s + 6

Operation:

GPR[rt] = effective_address(CPU.next_pc, s)

Exceptions:

Reserved Instruction for ADDIUPC[48] format on NMS cores.

Assembly:

ADDU dst, src1, src2

Purpose:

Add (Untrapped). Add two 32-bit integers in registers $src1 and $src2, placing the 32-bitresult in register $dst, and not trapping on overflow.

Availability:

nanoMIPS, availability varies by format.

Format:

ADDU[32]

dst = rd
src1 = rs
src2 = rt
not_in_nms = False

ADDU[16]

dst = decode_gpr(rd3, 'gpr3')
src1 = decode_gpr(rs3, 'gpr3')
src2 = decode_gpr(rt3, 'gpr3')
not_in_nms = False

ADDU[4X4], not available in NMS

dst = decode_gpr(rt4, 'gpr4')
src1 = decode_gpr(rt4, 'gpr4')
src2 = decode_gpr(rs4, 'gpr4')
not_in_nms = True

Operation:

if not_in_nms and C0.Config5.NMS:
    raise exception('RI')
sum = GPR[src1] + GPR[src2]
GPR[dst] = sign_extend(sum, from_nbits=32)

Exceptions:

Reserved Instruction for ADDU[4X4] format on NMS cores.

Assembly:

ALIGN rd, rs, rt, bp

Purpose:

Align. Concatenate the 32 bit values in registers $rt and $rs, extract the word at specifiedbyte position bp, and place the result in register $rd.

Availability:

Assembly alias

Expansion:

bp != 0:
EXTW rd, rs, rt, (4-bp)<<3
bp == 0:
MOVE rd, rt

Assembly:

ALUIPC rt, %pcrel_hi(address)

Purpose:

Add aLigned Upper Immediate to PC. Compute a 4KB aligned PC relative address by addingan upper 20 bitimmediate value to NextPC, discarding the lower 12 bits, and placing the resultin register $rt.

Availability:

nanoMIPS

Format:

offset = sign_extend(s, from_nbits=32)
address = effective_address(CPU.next_pc, offset) & ~0xfff

Operation:

GPR[rt] = address

Exceptions:

None.

Assembly:

AND rd, rs, rt

Purpose:

AND. Compute logical AND of registers $rs and $rt, placing the result in register $rd.

Availability:

nanoMIPS

Format:

AND[32]

AND[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
rd = rt

Operation:

GPR[rd] = GPR[rs] & GPR[rt]

Exceptions:

None.

Assembly:

ANDI rt, rs, u

Purpose:

AND Immediate. Compute logical AND of register $rs and immediate u, placing the resultin register $rt.

Availability:

nanoMIPS

Format:

ANDI[32]

ANDI[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
u = (0x00ff if eu == 12 else
     0xffff if eu == 13 else
     eu)

Operation:

GPR[rt] = GPR[rs] & u

Exceptions:

None.

Assembly:

BALC address

Purpose:

Branch And Link, Compact. Unconditional PC relative branch to address, placing returnaddress in register $31.

Availability:

nanoMIPS

Format:

BALC[32]

offset = sign_extend(s, from_nbits=26)

BALC[16]

offset = sign_extend(s, from_nbits=11)

Operation:

address = effective_address(CPU.next_pc, offset)
GPR[31] = CPU.next_pc
CPU.next_pc = address

Exceptions:

None.

Assembly:

BALRSC rt, rs

Purpose:

Branch And Link Register Scaled, Compact.

Unconditional branch to address NextPC+

2*$rs, placing return address in register $rt.

Availability:

nanoMIPS

Format:

Operation:

address = effective_address(CPU.next_pc, offset=GPR[rs]<<1)
GPR[rt] = CPU.next_pc
CPU.next_pc = address

Exceptions:

None.

Assembly:

BBEQZC rt, bit, address

Purpose:

Branch if Bit Equals Zero, Compact. PC relative branch to address if bit bit of register $rtis equal to zero.

Availability:

nanoMIPS, not available in NMS

Format:

offset = sign_extend(s, from_nbits=12)

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
if bit >= 32 and not Are64BitOperationsEnabled():
    raise exception('RI');
address = effective_address(CPU.next_pc, offset)
testbit = (GPR[rt] >> bit) & 1
if testbit == 0:
    CPU.next_pc = address

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

BBNEZC rt, bit, address

Purpose:

Branch if Bit Not Equal to Zero, Compact. PC relative branch to address if bit bit of register$rt is not equal to zero.

Availability:

nanoMIPS, not available in NMS

Format:

offset = sign_extend(s, from_nbits=12)

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
if bit >= 32 and not Are64BitOperationsEnabled():
    raise exception('RI');
address = effective_address(CPU.next_pc, offset)
testbit = (GPR[rt] >> bit) & 1
if testbit == 1:
    CPU.next_pc = address

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

BC address

Purpose:

Branch, Compact. Unconditional PC relative branch to address.

Availability:

nanoMIPS

Format:

BC[32]

offset = sign_extend(s, from_nbits=26)
address = effective_address(CPU.next_pc, offset)

BC[16]

offset = sign_extend(s, from_nbits=11)
address = effective_address(CPU.next_pc, offset)

Operation:

CPU.next_pc = address

Exceptions:

None.

Assembly:

BEQC rs, rt, address

Purpose:

Branch if Equal, Compact. PC relative branch to address if registers $rs and $rt are areequal.

Availability:

nanoMIPS, availability varies by format.

Format:

BEQC[32]

offset = sign_extend(s, from_nbits=15)
address = effective_address(CPU.next_pc, offset)
not_in_mms = False

BEQC[16], not available in NMS

rs = decode_gpr(rs3, 'gpr3')
rt = decode_gpr(rt3, 'gpr3')
offset = u
address = effective_address(CPU.next_pc, offset)
not_in_mms = True

Operation:

if not_in_mms and C0.Config5.NMS == 1:
    raise exception('RI')
if GPR[rs] == GPR[rt]:
    CPU.next_pc = address

Exceptions:

Reserved Instruction for BEQC[16] format on NMS cores.

Assembly:

BEQIC rt, u, address

Purpose:

Branch if Equal to Immediate, Compact. PC relative branch to address if value of register$rt is equal to immediate value u.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=12)
address = effective_address(CPU.next_pc, offset)
if GPR[rt] == u:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BEQZC rt, address # when rt andaddressarein range

Purpose:

Branch if Equal to Zero, Compact. PC relative branch to address if register $rt equals zero.

Availability:

nanoMIPS

Format:

BEQZC[16]

Operation:

rt = decode_gpr(rt3, 'gpr3')
offset = sign_extend(s, from_nbits=8)
address = effective_address(CPU.next_pc, offset)
if GPR[rt] == 0:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BGEC rs, rt, address

Purpose:

Branch if Greater than or Equal, Compact. PC relative branch to address if register $rs isgreater than or equal to register $rt.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=15)
address = effective_address(CPU.next_pc, offset)
if GPR[rs] >= GPR[rt]:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BGEIC rt, u, address

Purpose:

Branch if Greater than or Equal to Immediate, Compact. PC relative branch to address ifsigned register value $rt is greater than or equal to immediate u.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=12)
address = effective_address(CPU.next_pc, offset)
if GPR[rt] >= u:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BGEIUC rt, u, address

Purpose:

Branch if Greater than or Equal to Immediate Unsigned, Compact. PC relative branch toaddress if unsigned register $rt is greater than or equal to immediate u.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=12)
address = effective_address(CPU.next_pc, offset)
if unsigned(GPR[rt]) >= u:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BGEUC rs, rt, address

Purpose:

Branch if Greater than or Equal

to Unsigned, Compact.PC relative branch to address if

unsigned register $rs is greater than or equal to unsigned register $rt.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=15)
address = effective_address(CPU.next_pc, offset)
if unsigned(GPR[rs]) >= unsigned(GPR[rt]):
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BITREVB rt, rs

Purpose:

Bit Reverse in Bytes. Reverse bits in each byte of 32-bit value in register $rs, placing theresult in register $rt.

Availability:

Assembly alias, not available in NMS

Expansion:

ROTX rt, rs, 7, 8, 1

Assembly:

BITREVH rt, rs

Purpose:

Bit Reverse in Halfs. Reverse bits in each halfword of 32-bit value in register $rs, placingthe result in register $rt.

Availability:

Assembly alias, not available in NMS

Expansion:

ROTX rt, rs, 15, 16

Assembly:

BITREVW rt, rs

Purpose:

Bit Reverse in Word. Reverse all bits in 32 bit register $rs, placing the result in register $rt.

Availability:

Assembly alias, not available in NMS

Expansion:

ROTX rt, rs, 31, 0

Assembly:

BITSWAP rt, rs

Purpose:

Bitswap.

Reverse bits in each byte of 32-bit value in register $rs, placing the resultin

register $rt.

Availability:

Assembly alias, not available in NMS

Expansion:

ROTX rt, rs, 7, 8, 1

The assembly alias BITSWAP is provided for compatibility with MIPS32™.Its behavior is equivalent to the new assembly alias BITREVB, whose name is chosen to fit consistently with the naming of other

reversing instructions in nanoMIPS™.

Assembly:

BLTC rs, rt, address

Purpose:

Branch if Less Than, Compact. PC relative branch to address if signed register $rs is lessthan signed register $rt.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=15)
address = effective_address(CPU.next_pc, offset)
if GPR[rs] < GPR[rt]:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BLTIC rt, u, address

Purpose:

Branch if Less Than Immediate, Compact. PC relative branch to address if signed register$rt is less than immediate u.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=12)
address = effective_address(CPU.next_pc, offset)
if GPR[rt] < u:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BLTIUC rt, u, address

Purpose:

Branch if Less Than Immediate Unsigned Compact.

PC relative branch to address if unsigned register $rt is less than immediate u.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=12)
address = effective_address(CPU.next_pc, offset)
if unsigned(GPR[rt]) < u:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BLTUC rs, rt, address

Purpose:

Branch if Less Than Unsigned, Compact. PC relative branch to address if unsigned register$rs is less than unsigned register $rt.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=15)
address = effective_address(CPU.next_pc, offset)
if unsigned(GPR[rs]) < unsigned(GPR[rt]):
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BNEC rs, rt, address

Purpose:

Branch Not Equal, Compact. PC relative branch to address if register $rs is not equal toregister $rt.

Availability:

nanoMIPS, availability varies by format.

Format:

BNEC[32]

offset = sign_extend(s, from_nbits=15)

BNEC[16], not available in NMS

if C0.Config5.NMS == 1:
    raise exception('RI')
rs = decode_gpr(rs3, 'gpr3')
rt = decode_gpr(rt3, 'gpr3')
offset = u

Operation:

address = effective_address(CPU.next_pc, offset)
if GPR[rs] != GPR[rt]:
    CPU.next_pc = address

Exceptions:

Reserved Instruction for BNEC[16] format on NMS cores.

Assembly:

BNEIC rt, u, address

Purpose:

Branch if Not Equal to Immediate, Compact. PC relative branch to address if register $rt isnot equal to immediate u.

Availability:

nanoMIPS

Format:

Operation:

offset = sign_extend(s, from_nbits=12)
address = effective_address(CPU.next_pc, offset)
if GPR[rt] != u:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BNEZC rt, address

Purpose:

Branch if Not Equal to Zero, Compact. PC relative branch to address if register $rt is notequal to zero.

Availability:

nanoMIPS

Format:

BNEZC[16]

rt = decode_gpr(rt3, 'gpr3')
offset = sign_extend(s, from_nbits=8)

Operation:

address = effective_address(CPU.next_pc, offset)
if GPR[rt] != 0:
    CPU.next_pc = address

Exceptions:

None.

Assembly:

BREAK code

Purpose:

Break. Cause a Breakpoint exception.

Availability:

nanoMIPS

Format:

BREAK[32]

BREAK[16]

Operation:

raise exception('BP')

Exceptions:

Breakpoint.

Assembly:

BRSC rs

Purpose:

Branch Register Scaled, Compact. Unconditional branch to address

NextPC + 2*$rs.

Availability:

nanoMIPS

Format:

Operation:

address = effective_address(CPU.next_pc, offset=GPR[rs]<<1)
CPU.next_pc = address

Exceptions:

None.

Assembly:

BYTEREVH rt, rs

Purpose:

Byte Reverse in Halfs. Reverse bytes in each halfword of 32-bit value in register $rs, placingthe result in register $rt.

Availability:

Assembly alias, not available in NMS

Expansion:

ROTX rt, rs, 8, 24

Assembly:

BYTEREVW rt, rs

Purpose:

Byte Reverse in Word. Reverse each byte in word value in register $rs, placing the result inregister $rt.

Availability:

Assembly alias, not available in NMS

Expansion:

ROTX rt, rs, 24, 8

Assembly:

CACHE  op, offset(rs)

CACHEE op, offset(rs)

Purpose:

Cache operation/Cache operation using EVA addressing. Perform cache operation of typeop at address $rs +offset (register plus immediate). For CACHEE, translate the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Requires CP0 privilege, availability varies by format.

Format:

CACHE

offset = sign_extend(s, from_nbits=9)
is_eva = False

CACHEE, present when Config5.EVA=1.

offset = sign_extend(s, from_nbits=9)
is_eva = True

Operation:

# NMS core without caches gives RI (not CoprocessorUnusable)exception.
if (C0.Config5.NMS and C0.Config1.DL == 0 and C0.Config1.IL == 0
                   and C0.Config2.SL == 0 and C0.Config2.TL == 0
                   and C0.Config5.L2C == 0):
    raise exception('RI')
if is_eva and not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=is_eva)
# Behavior for index cacheops is unpredictable ifaddressisnotunmapped.
if op <= 11:  # Index cacheop
    translation_type, description, result_args = decode_va(va, eva=is_eva)
    if translation_type != 'unmapped':
        raise UNPREDICTABLE('Index cacheopunpredictable withVA not unmapped')
pa, cca = va2pa(va, 'Cacheop', eva=is_eva)
if cca == 2 or cca == 7:
    if C0.Config.AT >= 2:
        pass  # Cacheop to uncached address is anopin R6
    else:
        raise UNPREDICTABLE('Cacheop to uncached address isunpredictable')
else:
    cacheop(va, pa, op)

The CACHE/CACHEE instructions perform the cache operation specified by argument ’op’ on the register plus immediate address $rs +offset. For CACHEE, the virtual address is translated as though

the core is in user mode, although it is actually in kernel mode.

The ’op’ argument is a 5 bit value specifying one of the following the possible cache operations, which are described in more detail below:

’op’OperationAvailability

0ICache Index InvalidateRequired (if ICache present) 1DCache Index Writeback InvalidateRequired (if DCache present)

2TCache Index Writeback InvalidateRequired (if TCache present) 3SCache Index Writeback InvalidateRequired (if SCache present)

4ICache Index Load TagRecommended (if ICache present) 5DCache Index Load TagRecommended (if DCache present)

6TCache Index Load TagRecommended (if TCache present) 7SCache Index Load TagRecommended (if SCache present)

8ICache Index Store TagRequired (if ICache present) 9DCache Index Store TagRequired (if DCache present)

10TCache Index Store TagRequired (if TCache present) 11SCache Index Store TagRequired (if SCache present)

12ICache Implementation Dependent OpOptional (if ICache present) 13DCache Implementation Dependent OpOptional (if DCache present)

14TCache Implementation Dependent OpOptional (if TCache present) 15SCache Implementation Dependent OpOptional (if SCache present)

16ICache Hit InvalidateRequired (if ICache present) 17DCache Hit InvalidateOptional (if DCache present)

18TCache Hit InvalidateOptional (if TCache present) 19SCache Hit InvalidateOptional (if SCache present)

20ICache FillRecommended (if ICache present) 21DCache Hit Writeback InvalidateRecommended (if DCache present)

’op’OperationAvailability

22TCache Hit Writeback InvalidateRecommended (if TCache present) 23SCache Hit Writeback InvalidateRecommended (if SCache present)

24Unused 25DCache Hit WritebackRecommended (if DCache present)

26TCache Hit WritebackRecommended (if TCache present) 27SCache Hit WritebackRecommended (if SCache present)

28ICache Fetch and LockRecommended (if ICache present) 29DCache Fetch and LockRecommended (if DCache present)

30Unused 31Unused

Index cacheops (those with op <= 11 and optionally the implementation dependent cases 12<= op <=

15) are operations where the input address is treated as an index into the target cache array. The rules for constructing the index are given in the cacheop() function pseudocode.

’Hit’ cacheops are operations where the input address is treated as a virtual memory address.The operation willtargetthe cache line containing data for that virtual address,ifitis presentin the

cache.

The operations listed above behave as follows:

• ICache Index Invalidate (op=0): Set the state of the instruction cache line at the specified index to invalid.

• D/T/S Cache Index Writeback Invalidate (op=1,2,3):

Ifthe cache line atthe specified index is

valid and dirty, write the line back to the memory address specified by the cache tag. Whether or not the line was dirty, set the state of the cache line to invalid. For a write-through cache, the

writeback step is not required and this is effectively a Cache Index Invalidate operation. This cache operation is required and may be used by software to invalidate the entire data cache by

stepping through allindices. Note that the Index Store Tag operation must be used to initialize the cache at power up.

• I/D/T/S Cache Index Load Tag (op=4,5,6,7): Read the tag for the cache line at the specified index

into the TagLo and TagHi Coprocessor 0 registers.If the DataLo and DataHi registers are implemented, also read the data corresponding to the byte index into the DataLo and DataHi registers.

This operation must not cause a Cache Error Exception. The granularity and alignment of the data read into the DataLo and DataHi registers is implementation-dependent, but is typically the

result of an aligned access to the cache, ignoring the appropriate low-order bits of the byte index.

• I/D/T/S Cache Index Store Tag (op=8,9,10,11): Write the tag for the cache block at the specified index from the TagLo and TagHi Coprocessor 0 registers. This operation must not cause a Cache

Error Exception. This required encoding may be used by software to initialize the entire instruction or data caches by stepping through all valid indices. Doing so requires that the TagLo and

TagHi registers associated with the cache be initialized to zero first.

• I/D/T/S Cache Implementation Dependent Op (op=12,13,14,15): Available for implementation dependent operation.

• I/D/T/S Cache Hit Invalidate (op=16,17,18,19):

If the cache block contains the specified address,

setthe state ofthe cache block to invalid.This required encoding may be used by software to invalidate a range of addresses from the instruction cache by stepping through the address

range by the line size of the cache.In multiprocessor implementations with coherent caches, the operation may optionally be broadcast to all coherent caches within the system.

• ICache FIll (op=20): Fill the cache from the specified virtual address.

• D/T/S Hit Writeback Invalidate (op=21,22,23): For the cache line (if any) which contains the

specified address:if the cache line is valid and dirty, write the line back to the memory address specified by the cache tag. Whether or not the line was dirty, set the state of the cache line to

invalid. For a write-through cache,the writeback step is not required and this is effectively a Cache Hit Invalidate operation. This cache operation is required and may be used by software to

invalidate a range of addresses from the data cache by stepping through the address range by the line size of the cache.In multiprocessor implementations with coherent caches, the operation

may optionally be broadcast to all coherent caches within the system.

• D/T/S Hit Writeback (op=25,26,27):

If the cache block contains the specified address and it is

valid and dirty, write the contents back to memory. After the operation is completed,leave the state of the line valid, but clear the dirty state. For a write-through cache, this operation may be

treated as a nop.In multiprocessor implementations with coherent caches, the operation may optionally be broadcast to all coherent caches within the system.

• I/D Fetch and Lock (op=28,29):

If the cache does not contain the specified virtual address, fill

itfrom memory, performing a write-back if required.Setthe state to valid and locked.The way selected on a fill from memory is implementation dependent. The lock state may be cleared

by executing an Index Invalidate,Index Writeback Invalidate, Hit Invalidate, or Hit Writeback Invalidate operation to the locked line, or via an Index Store Tag operation to the line that clears

the lock bit.It is implementation dependent whether a locked line is displaced as the result of an external invalidate or intervention that hits on the locked line. Software must not depend on the

locked line remaining in the cache if an externalinvalidate or intervention would invalidate the line if it were not locked.It is implementation dependent whether a Fetch and Lock operation

affects more than one line. For example, more than one line around the referenced address may be fetched and locked.Itis recommended that only the single line containing the referenced

address be affected.

It is implementation dependent whether the input address for an Index cacheop is converted into a physical address by the MMU, so to avoid the posibility of generating a TLB exception, the index value

should always be converted to an unmapped address (such as a kseg0 address by ORing the index with 0x80000000) before being used by the cache instruction. For example, the following code sequence

performs a data cache Index Store Tag operation using the index passed in GPR a0:

        li      a1, 0x80000000       /* Baseofkseg0 segment */
        or      a0, a0, a1           /* Convertindex to kseg0 address */
        cache   DCIndexStTag, 0(a1)  /* Performtheindex store tag operation */

Some CACHE/CACHEE operations may result in a Cache Error exception. For example, if a Writeback operation detects a cache or bus error during the processing of the operation, that error is reported

via a Cache Error exception.Also, a Bus Error Exception may occur if a bus operation invoked by this instruction is terminated in an error. However, cache error exceptions must not be triggered by

an Index Load Tag or Index Store tag operation, as these operations are used for initialization and diagnostic purposes.

It is implementation dependent whether a data watch is triggered by a cache instruction whose address matches the Watch register address match conditions. The preferred implementation is not to match

on the CACHE/CACHEE instructions.

The operation of the instruction is UNPREDICTABLE if the cache line that contains the CACHE instruction is the target of an invalidate or a writeback invalidate operation.

If this instruction is used to lock all ways of a cache at a specific cache index, the behavior of that cache to subsequent cache misses to that cache index is UNDEFINED.

The effective address may be arbitrarily aligned. The CACHE/CACHEE instructions never causes an Address Error Exception due to a non-aligned address.

The CACHE instruction and the memory transactions which are sourced by the CACHE instruction, such as cache refill or cache writeback, obey the ordering and completion rules of the SYNC instruction.

Any use of this instruction that can cause cacheline writebacks should be followed by a subsequent SYNC instruction to avoid hazards where the writeback data is not yet visible at the next level of the

memory hierarchy.

For multiprocessor implementations that maintain coherent caches, some of the Hit type operations

may optionally affect all coherent caches within the implementation.In this case,if the effective address uses a coherent Cache Coherency Attribute (CCA),

then the operation is globalized, meaning

it is broadcast to all of the coherent caches within the system.If the effective address does not use one of the coherent CCAs, there is no broadcast of the operation.If multiple levels of caches are to

be affected by one CACHE instruction, all of the affected cache levels must be processed in the same manner - either all affected cache levels use the globalized behavior or all affected cache levels use

the non-globalized behavior.

Exceptions:

Address Error. Bus Error. Cache Error. Coprocessor Unusable. Reserved Instruction on NMS cores without caches. Reserved Instruction for CACHEE if EVA not implemented. TLB Invalid. TLB Refill.

Assembly:

CLO rt, rs

Purpose:

Count Leading Ones. Count leading ones in 32-bit register value $rs, placing the result inregister $rt.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
input = GPR[rs]
i = 0
while i < 32:
    if input[31 - i] != 1: break
    i += 1
GPR[rt] = i

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

CLZ rt, rs

Purpose:

Count Leading Zeros. Count leading zeros in 32-bit register value $rs, placing the result inregister $rt.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
input = GPR[rs]
i = 0
while i < 32:
    if input[31 - i] != 0: break
    i += 1
GPR[rt] = i

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

CRC32B rt, rs

Purpose:

CRC32 Byte.Generatea32-bit CRC valuebasedonthereversedpolynomial$rt

0xEDB88320,using cumulative 32-bit CRC valueand right-justified byte-sized message$rt $rs as inputs.

Availability:

nanoMIPS. Optional, present when Config5.CRCP=1.

Format:

Operation:

if C0.Config5.CRCP == 0:
    raise exception('RI')
result = crc32(value=GPR[rt], message=GPR[rs], nbits=8, poly=0xEDB88320)
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction on cores without CRC support.

Assembly:

CRC32CB rt, rs

Purpose:

CRC32 (Castagnoli) Byte. Generate a 32-bit CRC value $rt based on the reversed polynomial0x82F63B78, using cumulative 32-bit CRC value $rt and right-justified byte-sized message $rs as inputs.

Availability:

nanoMIPS. Optional, present when Config5.CRCP=1.

Format:

Operation:

if C0.Config5.CRCP == 0:
    raise exception('RI')
result = crc32(value=GPR[rt], message=GPR[rs], nbits=8, poly=0x82F63B78)
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction on cores without CRC support.

Assembly:

CRC32CH rt, rs

Purpose:

CRC32 (Castagnoli) Half. Generate a 32-bit CRC value $rt based on the reversed polynomial0x82F63B78, using cumulative 32-bit CRC value $rt and right-justified halfword-sized message $rs as inputs.

Availability:

nanoMIPS. Optional, present when Config5.CRCP=1.

Format:

Operation:

if C0.Config5.CRCP == 0:
    raise exception('RI')
result = crc32(value=GPR[rt], message=GPR[rs], nbits=16, poly=0x82F63B78)
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction on cores without CRC support.

Assembly:

CRC32CW rt, rs

Purpose:

CRC32 (Castagnoli) Word. Generate a 32-bit CRC value $rt based on the reversed polynomial 0x82F63B78, using cumulative 32-bit CRC value $rt and right-justified word-sized message $rs as inputs.

Availability:

nanoMIPS. Optional, present when Config5.CRCP=1.

Format:

Operation:

if C0.Config5.CRCP == 0:
    raise exception('RI')
result = crc32(value=GPR[rt], message=GPR[rs], nbits=32, poly=0x82F63B78)
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction on cores without CRC support.

Assembly:

CRC32H rt, rs

Purpose:

CRC32 Half.Generatea32-bit CRC valuebasedonthereversedpolynomial$rt

0xEDB88320,using cumulative 32-bit CRC valueand right-justified halfword-sized message$rt

$rs as inputs.

Availability:

nanoMIPS. Optional, present when Config5.CRCP=1.

Format:

Operation:

if C0.Config5.CRCP == 0:
    raise exception('RI')
result = crc32(value=GPR[rt], message=GPR[rs], nbits=16, poly=0xEDB88320)
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction on cores without CRC support.

Assembly:

CRC32W rt, rs

Purpose:

CRC32 Word.Generatea 32-bit CRC value$rt based on thereversed polynomial

0xEDB88320, using cumulative 32-bit CRC value $rt and right-justified word-sized message $rs as inputs.

Availability:

nanoMIPS. Optional, present when Config5.CRCP=1.

Format:

Operation:

if C0.Config5.CRCP == 0:
    raise exception('RI')
result = crc32(value=GPR[rt], message=GPR[rs], nbits=32, poly=0xEDB88320)
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction on cores without CRC support.

Assembly:

DERET

Purpose:

Debug Exception Return. Return from a debug exception by jumping to the address in theDEPC register, and clearing Debug.DM.

Availability:

nanoMIPS. Optional, present when Debug implemented.

Format:

Operation:

if C0.Config1.EP == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if C0.Debug.DM == 0:
    raise exception('RI')
CPU.next_pc = sign_extend(Root.C0.DEPC)
C0.Debug.DM = 0
# If single stepping, forward progress isallowedonthenextinstruction.
CPU.debug_sst_progress_allowed = True
clear_execution_hazards()
clear_instruction_hazards()

The DERET instruction implements a software barrier that resolves all execution and instruction hazards. See the EHB and JALRC.HB instructions for an explanation of execution and instruction hazards

respectively, and also the SYNCI/SYNCIE instruction for additionalinformation on resolving instruction hazards created by writing to the instruction stream.

The effects of the DERET barrier are seen starting with the fetch and decode of the instruction at the PC to which the DERET returns. This means,for instance,that if C0.DEPC is modified by an MTC0

instruction prior to a DERET, an EHB is required between the MTC0 and the DERET to ensure that the DERET uses the correct DEPC value.

The DERET instruction is only legalin debug mode and will give a Coprocessor Unusable exception when executed in user mode or a Reserved Instruction exception when executed in kernel mode.

Exceptions:

Coprocessor Unusable.Reserved Instruction when notin Debug Mode or on cores without Debug support.

Assembly:

DI rt

Purpose:

Disable Interrupts. Disable interrupts by setting Status.IE to 0, and return the previousvalue of Status register in register $rt.

Availability:

nanoMIPS. Requires CP0 privilege.

Format:

Operation:

if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
GPR[rt] = C0.Status
C0.Status.IE = 0

Exceptions:

Coprocessor Unusable.

Assembly:

DIV rd, rs, rt

Purpose:

Divide. Divide signed word $rs by signed word $rt and place the result in $rd.

Availability:

nanoMIPS

Format:

Operation:

numerator = GPR[rs]
denominator = GPR[rt]
if denominator == 0:
    quotient, remainder = (UNKNOWN, UNKNOWN)
else:
    quotient, remainder = divide_integers(numerator, denominator)
GPR[rd] = sign_extend(quotient, from_nbits=32)

Exceptions:

None.

Assembly:

DIVU rd, rs, rt

Purpose:

Divide Unsigned. Divide unsigned word $rs by unsigned word $rt and place the result inregister $rd.

Availability:

nanoMIPS

Format:

Operation:

numerator = zero_extend(GPR[rs], from_nbits=32)
denominator = zero_extend(GPR[rt], from_nbits=32)
if denominator == 0:
    quotient, remainder = (UNKNOWN, UNKNOWN)
else:
    quotient, remainder = divide_integers(numerator, denominator)
GPR[rd] = sign_extend(quotient, from_nbits=32)

Exceptions:

None.

Assembly:

DVP rt

Purpose:

Disable Virtual Processors. Disable all virtual processors in a physical core other than theone that issued the instruction. Set VPControl.DIS to 1, and place the previous value of the VPControl CP0 register in register $rt.

Availability:

nanoMIPS. Optional, present when Config5.VP=1, otherwise NOP. Requires CP0 privilege.

Format:

Operation:

if C0.Config5.VP == 0:
    # No operation when VP not implemented pass
else:
    if not IsCoprocessor0Enabled():
        raise coprocessor_exception(0)
    GPR[rt] = C0.VPControl
    C0.VPControl.DIS = 1
    disable_virtual_processors()

The DVP instruction is used to halt instruction fetch for all virtual processors in a VP core, other than the one which issued the DVP instruction. Possible uses for DVP include:

• Performing cache operations where the cache state must not be affected by the actions of other

threads on the same core.

• Reprogramming virtual processor scheduling priority.

All outstanding instructions for the affected virtual processors must be complete before the DVP itself is allowed to retire. Any outstanding events such as hardware instruction or data prefetch, or page-table

walks, must also be terminated.

Memory ordering equivalent to that provided by SYNC(stype=0) is guaranteed between subsequent

instructions on the virtual processor which issued the DVP, and instructions which have already graduated on the disabled virtual processors.

If a virtual processor is already disabled by another event,for instance,if it has executed a WAIT or a PAUSE instruction or has been halted by some external hardware event,then the disabled virtual

processor will not be re-enabled until both an EVP instruction has been executed on the controlling thread, and an event which would otherwise have woken the virtual processor (such as an interrupt for

a WAIT instruction or an interrupt or clearing of the LLBit for a PAUSE instruction) has also occurred.

The effect of a DVP instruction is undone by an EVP instruction, which causes execution to resume immediately (where applicable) on all other virtual processors. From the perspective of the disabled

virtual processors, after the EVP, execution continues as though the DVP had not occurred.

If an event occurs in between the DVP and EVP that renders state of a disabled virtual processor UNPREDICTABLE (such as power-gating), then the effect of EVP is UNPREDICTABLE.

A disabled virtual processor cannot be woken by an interrupt or a deferred exception, at least until execution is re-enabled by an EVP instruction on the controlling thread.The virtual processor that

executes the DVP, however, continues to be interruptible.

A DVP which is executed when VPControl.DIS=1 will return the current value of the VPControl register but otherwise will leave the other virtual processors in a disabled state. Software should only re-enable

virtual processors (via the EVP instruction) if it has verified from the VPControl value returned by the DVP that virtual processors were previously enabled. Performing this check allows DVP/EVP pairs to

be safely nested.

In a core with multiple virtual processors, more than one virtual processor may execute a DVP simultaneously. The implementation should ensure that the selection of which virtual processor’s DVP successfully graduates is not biased towards any one virtual processor, in order to prevent the possibility

of live-lock.

The DVP instruction behaves like a NOP on cores which do not implement virtual processors (i.e. when Config5.VP=0). This behavior allows kernel code to enclose critical sequences within DVP/EVP blocks

without first checking whether itis running on a VP core.The encoding ofthe DVP instruction is equivalentto a SLTU instruction targeting $0,i.e.a NOP, which leads to the correct behavior on

non-VP cores with no additional hardware special casing.

Exceptions:

Coprocessor Unusable.

Assembly:

EHB

Purpose:

Execution hazard barrier. Clear all execution hazards before allowing any subsequent instructions to graduate.

Availability:

nanoMIPS

Format:

Operation:

clear_execution_hazards()

The EHB instruction creates an execution hazard barrier, meaning thatit ensures that subsequent

instructions will be aware of changes to CP0 state caused by prior instructions. Examples of instructions which change CP0 state and which need an execution hazard barrier to ensure that subsequent

instructions see those updates are MTC0, EI, DI, TLBR and CACHE/CACHEE

In the absence of an execution hazard barrier, the CP0 register value used as input to an instruction may be out of date, since it may have been read before the write to the CP0 register by a prior instruction

has actually been committed.

An execution hazard barrier is sufficient to ensure that a fetched instruction is aware of all prior CP0 updates. However, it is not sufficient to ensure that the correct instruction is being fetched as a result

of those CP0 updates. Ensuring that the correct instruction is fetched requires an instruction hazard barrier, which is provided by the JALRC.HB instruction, or any ofthe exception return instructions

ERET/ERETNC or DERET.

Exceptions:

None.

Assembly:

EI rt

Purpose:

Enable Interrupts.

Enable interrupts by setting Status.IE to 1, and return the previous

value of Status register in register $rt.

Availability:

nanoMIPS. Requires CP0 privilege.

Format:

Operation:

if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
GPR[rt] = C0.Status
C0.Status.IE = 1

Exceptions:

Coprocessor Unusable.

Assembly:

ERET

ERETNC

Purpose:

Exception Return/Exception Return Not Clearing LLBit. Return from an exception: either byclearing Status.ERL if set and jumping to the address in ErrorEPC; otherwise by clearing Status.EXL,

jumping to the address in EPC, and updating the current Shadow Register Setto SRSCtl.PSS if required.

Availability:

nanoMIPS, availability varies by format.

Format:

ERET, requires CP0 privilege.

nc = False

ERETNC, present when Config5.LLB=1. Requires CP0 privilege.

nc = True

Operation:

if nc and C0.Config5.LLB == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if C0.Status.ERL == 1:
    effective_epc = sign_extend(C0.ErrorEPC)
    C0.Status.ERL = 0
else:
    effective_epc = sign_extend(C0.EPC)
    C0.Status.EXL = 0
    if C0.SRSCtl.HSS > 0 and C0.Status.BEV == 0:
        C0.SRSCtl.CSS = C0.SRSCtl.PSS
CPU.next_pc = effective_epc
# clear LLbit unless this is an ERETNC
if not nc:
   C0.LLAddr.LLB = 0
clear_execution_hazards()
clear_instruction_hazards()

The ERET/ERETNC instructions implement a software barrier that resolves all execution and instruction hazards. See the EHB and JALRC.HB instructions for an explanation of execution and instruction

hazards respectively, and also the SYNCI/SYNCIE instruction for additionalinformation on resolving instruction hazards created by writing to the instruction stream.

The effects of the ERET/ERETNC barrier are seen starting with the fetch and decode of the instruction at the PC to which the ERET returns. This means, for instance, that if C0.EPC is modified by an MTC0

instruction prior to an ERET, an EHB is required between the MTC0 and the ERET to ensure that the ERET uses the correct EPC value.

Config5.LLB indicates support for the ERETNC instruction.It is always 1 for R6 cores, except for those implementing the nanoMIPS™ subset.In other words, ERETNC is required for nanoMIPS™ cores and

optional for NMS cores.

Exceptions:

Coprocessor Unusable. Reserved Instruction allowed for ERETNC on NMS cores.

Assembly:

EVP rt

Purpose:

Enable VirtualProcessors.Enableallvirtualprocessorsinaphysicalcore.Set

VPControl.DIS to 0, and place the previous value of the VPControl CP0 register in register $rt.

Availability:

nanoMIPS. Optional, present when Config5.VP=1, otherwise NOP. Requires CP0 privilege.

Format:

Operation:

if C0.Config5.VP == 0:
    # No operation when VP not implemented pass
else:
    if not IsCoprocessor0Enabled():
        raise coprocessor_exception(0)
    GPR[rt] = C0.VPControl
    C0.VPControl.DIS = 0
    enable_virtual_processors()

The EVP instruction is used on VP cores to undo the effect of a DVP instruction, and the reader should refer to the DVP description for details regarding its usage.

The EVP instruction behaves like a NOP on cores which do not implement virtual processors (i.e. when Config5.VP=0). This behavior allows kernel code to enclose critical sequences within DVP/EVP blocks

without first checking whether itis running on a VP core.The encoding ofthe EVP instruction is equivalentto a SLTU instruction targeting $0,i.e.a NOP, which leads to the correct behavior on

non-VP cores with no additional hardware special casing.

Exceptions:

Coprocessor Unusable.

Assembly:

EXT rt, rs, pos, size

Purpose:

Extract. Extract a bit field of size size at position pos from register $rs and store it rightjustified into register $rt.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
pos = lsb
size = msbd + 1
if pos + size > 32:
    raise UNPREDICTABLE()
result = zero_extend(GPR[rs] >> pos, from_nbits=size)
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

EXTW rd, rs, rt, shift

Purpose:

Extract Word. Concatenate the 32 bit values in registers $rt and $rs, extract the word atspecified bit position shift, and place the result in register $rd.

Availability:

nanoMIPS

Format:

Operation:

tmp = GPR[rt][31:0] @ GPR[rs][31:0]
result = tmp >> shift
GPR[rd] = sign_extend(result, from_nbits=32)

Exceptions:

None.

Assembly:

GINVI rs

Purpose:

Globally Invalidate Instruction caches.

Availability:

nanoMIPS. Optional, present when

Config5.GI >= 2. Requires CP0 privilege.

Format:

Operation:

if C0.Config5.GI < 2:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if GPR[rs] == 0:
    cores = get_all_cores_in_system()
else:
    cores = implementation_dependent_ginvi_cores(GPR[rs])
for core in cores:
    # Find encoded line size, sets, and associativity for thetargetcache.
    (L, S, A) = get_cache_parameters('I', core)
    num_sets = 2 ** (S + 6)
    num_ways = A + 1
    for way_index in range(num_ways):
        for set_index in range(num_sets):
            cache_line = get_cache_line('I', way_index,set_index, core)
            cache_line.valid = False

When $rs is 0, GINVI fully invalidates allinstruction caches of all cores in the system,including the localinstruction cache. For non-zero $rs values, GINVI invalidates the instruction cache of a specific,

implementation dependent core in the system.

The GINVIinstruction must be followed by a SYNC (stype=0x14) and an instruction hazard barrier (e.g.JRC.HB) to ensure that all instruction caches in the system have been invalidated.

Exceptions:

Coprocessor Unusable. Reserved Instruction if Global Invalidate I-cache not implemented.

Assembly:

GINVT rs, type

Purpose:

Globally invalidate TLBs.

Availability:

nanoMIPS. Optional, present when Config5.GI=3. Requires CP0 privilege.

Format:

Operation:

if C0.Config5.GI != 3:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if not C0.Config5.MI:
    raise exception('RI', 'Config5.MI notset')
ginvt(type, va=GPR[rs])

Perform type invalidation of all TLBs in the system, where type is one of:

•      type=0:
  

invALL - invalidate all non wired entries.

•      type=1:
  

invVA- invalidate all entries which match the VA specified by $rs.

•      type=2:
  

invMMID invalidate all entries which match C0.MemoryMapID.MMID and are not

global.

•      type=3:
  

invVAMMID - invalidate all entries which match the VA specified by $rs and either match

C0.MemoryMapID or are global.

The GINVT instruction must be followed by a SYNC (stype=0x14) and an instruction hazard barrier (e.g.JRC.HB) to ensure that matching entries have been removed from all TLBs in the system and that

all instructions in the instruction stream can only access the new context.

invMMID and invVAMMID operations use the C0.MemoryMapID value of the currently running process. The kernel must save/restore C0.MemoryMapID appropriately before it modifies it for the invalidation

operation. Between the save and restore, it must utilize unmapped addresses.

Exceptions:

Coprocessor Unusable.Reserved Instruction if GlobalInvalidate TLB notimplemented.Reserved Instruction if MemoryMapID not enabled (i.e. Config5.MI==0).

Assembly:

INS rt, rs, pos, size

Purpose:

Insert. Merge a right justified bit field of size size from register $rs into position pos of

register $rt.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
pos = lsb
size = 1 + msbd - lsb
if size < 1:
    raise UNPREDICTABLE()
merge_mask = ((1<<size) - 1) << pos
result = (GPR[rt] & ~merge_mask
          | (GPR[rs] << pos) & merge_mask)
GPR[rt] = sign_extend(result, from_nbits=32)

The INS instruction is not available on NMS cores.It can be emulated using a sequence of three EXTW instructions:

       INS      rt, rs, pos, size

can be emulated using the following sequence of instructions (provided rt is not equal to rs):

       EXTW     rt, rt, rt, pos
       EXTW     rt, rt, rs, size
       EXTW     rt, rt, rt, 32 size -pos

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

JALRC.HB rt, rs

Purpose:

Jump And Link Register, Compact, with Hazard Barrier. Unconditionaljump to address in

register $rs, placing the return address in register $rt. Clear allinstruction and execution hazards before allowing any subsequent instructions to graduate.

Availability:

nanoMIPS

Format:

Operation:

address = GPR[rs] + 0
GPR[rt] = CPU.next_pc
CPU.next_pc = address
clear_instruction_hazards()
clear_execution_hazards()

The JALRC.HB instruction creates an instruction hazard barrier, meaning that it ensures that subsequent

instruction fetches will be aware of state changes caused by prior instructions.Examples of

state changes which affect instruction fetch and which need an instruction hazard barrier to ensure that subsequent instructions see those updates are:

• Writes to the instruction stream (which must also have been synchronized by a SYNCI/SYNCIE

and a SYNC).

• Updates to the TLB.

• Changes in CP0 state which affect addresses mappings.

In the absence of an instruction hazard barrier, the state used as input to an instruction fetch may be out of date, since it may have been read before the updates to that state have actually completed.

JALRC.HB also provides an execution hazard barrier, see the EHB instruction definition for details. An instruction hazard barrier is also provided by any of the exception return instructions ERET/ERETNC,

or DERET, but those instructions are only available to privileged software, whereas JALRC.HB is available from all operating modes.

Exceptions:

None.

Assembly:

JALRC dst, src

Purpose:

Jump And Link Register, Compact. Unconditionaljump to address in register $src, placing

the return address in register $dst.

Availability:

nanoMIPS

Format:

JALRC[32]

src = rs
dst = rt

JALRC[16]

src = rt
dst = 31

Operation:

address = GPR[src] + 0
GPR[dst] = CPU.next_pc
CPU.next_pc = address

Exceptions:

None.

Assembly:

JRC rt

Purpose:

Jump Register, Compact. Unconditional jump to address in register $rt.

Availability:

nanoMIPS

Format:

Operation:

address = GPR[rt]
CPU.next_pc = address

Exceptions:

None.

Assembly:

LAPC rt, address

Purpose:

Load Address, PC relative. Load PC relative address to register $rt.

Availability:

Assembly alias. NMS cores restricted to 21 bit signed offset from PC.

Expansion:

address = $PC + imm (imm in 21 bit signed range):
ADDIUPC[32] rt, imm
address = $PC + imm (imm in 32 bit signed range):
ADDIUPC[48] rt, imm

LAPC uses the ADDIUPC instruction to load a PC relative address into register $rt.In order to determine the correct immediate value for the ADDIUPC instruction, the assembler must assume a value

for the PC that the instruction will be executed from.If the instruction is executed from a different PC, then the generated address will be shifted by a PC relative amount.

Assembly:

LB rt, offset(rs)

Purpose:

Load Byte. Load signed byte to register $rt from memory address $rs + offset (registerplus immediate).

Availability:

nanoMIPS

Format:

LB[U12]

offset = u

LB[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
offset = u

LB[GP]

rs = 28
offset = u

LB[S9]

offset = sign_extend(s, from_nbits=9)

Operation:

va = effective_address(GPR[rs], offset, 'Load')
data = read_memory_at_va(va, nbytes=1)
GPR[rt] = sign_extend(data, from_nbits=8)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LBE rt, offset(rs)

Purpose:

Load Byte using EVA addressing. Load signed byte to register $rt from virtual address $rs+ offset, translating the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege.

Format:

Operation:

offset = sign_extend(s, from_nbits=9)
if not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=True)
data = read_memory_at_va(va, nbytes=1, eva=True)
GPR[rt] = sign_extend(data, from_nbits=8)

Exceptions:

Address Error. Bus Error. Coprocessor Unusable. Reserved Instruction if EVA not implemented. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LBU rt, offset(rs)

Purpose:

Load Byte Unsigned. Load unsigned byte to register $rt from memory address $rs + offset(register plus immediate).

Availability:

nanoMIPS

Format:

LBU[U12]

offset = u

LBU[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
offset = u

LBU[GP]

rs = 28
offset = u

LBU[S9]

offset = sign_extend(s, from_nbits=9)

Operation:

va = effective_address(GPR[rs], offset, 'Load')
GPR[rt] = read_memory_at_va(va, nbytes=1)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LBUE rt, offset(rs)

Purpose:

Load Byte Unsigned using EVA addressing. Load unsigned byte to register $rt from virtualaddress $rs + offset, translating the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege.

Format:

Operation:

offset = sign_extend(s, from_nbits=9)
if not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=True)
GPR[rt] = read_memory_at_va(va, nbytes=1, eva=True)

Exceptions:

Address Error. Bus Error. Coprocessor Unusable. Reserved Instruction if EVA not implemented. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LBUX rd, rs(rt)

Purpose:

Load Byte Unsigned indeXed. Load unsigned byte to register $rd from memory address $rt+ $rs (register plus register).

Availability:

nanoMIPS

Format:

Operation:

va = effective_address(GPR[rs], GPR[rt], 'Load')
GPR[rd] = read_memory_at_va(va, nbytes=1)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LBX rd, rs(rt)

Purpose:

Load Byte indeXed. Load signed byte to register $rd from memory address $rt + $rs (register plus register).

Availability:

nanoMIPS

Format:

Operation:

va = effective_address(GPR[rs], GPR[rt], 'Load')
data = read_memory_at_va(va, nbytes=1)
GPR[rd] = sign_extend(data, from_nbits=8)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LH rt, offset(rs)

Purpose:

Load Half. Load signed halfword to register $rt from memory address $rs + offset (registerplus immediate).

Availability:

nanoMIPS

Format:

LH[U12]

offset = u

LH[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
offset = u

LH[GP]

rs = 28
offset = u

LH[S9]

offset = sign_extend(s, from_nbits=9)

Operation:

va = effective_address(GPR[rs], offset, 'Load')
data = read_memory_at_va(va, nbytes=2)
GPR[rt] = sign_extend(data, from_nbits=16)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LHE rt, offset(rs)

Purpose:

Load Half using EVA addressing. Load signed halfword to register $rt from virtual address$rs + offset, translating the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege.

Format:

Operation:

if not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
offset = sign_extend(s, from_nbits=9)
va = effective_address(GPR[rs], offset, 'Load', eva=True)
data = read_memory_at_va(va, nbytes=2, eva=True)
GPR[rt] = sign_extend(data, from_nbits=16)

Exceptions:

Address Error. Bus Error. Coprocessor Unusable. Reserved Instruction if EVA not implemented. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LHU rt, offset(rs)

Purpose:

Load Half Unsigned. Load unsigned halfword to register $rt from memory address $rs +offset (register plus immediate).

Availability:

nanoMIPS

Format:

LHU[U12]

offset = u

LHU[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
offset = u

LHU[GP]

rs = 28
offset = u

LHU[S9]

offset = sign_extend(s, from_nbits=9)

Operation:

va = effective_address(GPR[rs], offset, 'Load')
GPR[rt] = read_memory_at_va(va, nbytes=2)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LHUE rt, offset(rs)

Purpose:

Load Half Unsigned using EVA addressing. Load unsigned halfword to register $rt from virtual address $rs + offset, translating the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege.

Format:

Operation:

if not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
offset = sign_extend(s, from_nbits=9)
va = effective_address(GPR[rs], offset, 'Load', eva=True)
GPR[rt] = read_memory_at_va(va, nbytes=2, eva=True)

Exceptions:

Address Error. Bus Error. Coprocessor Unusable. Reserved Instruction if EVA not implemented. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LHUX rd, rs(rt)

Purpose:

Load Half Unsigned indeXed. Load unsigned halfword to register $rd from memory address$rt + $rs (register plus register).

Availability:

nanoMIPS

Format:

Operation:

va = effective_address(GPR[rs], GPR[rt], 'Load')
GPR[rd] = read_memory_at_va(va, nbytes=2)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LHUXS rd, rs(rt)

Purpose:

Load Half Unsigned indeXed Scaled. Load unsigned halfword to register $rd from memoryaddress $rt + 2*$rs (register plus scaled register).

Availability:

nanoMIPS

Format:

Operation:

va = effective_address(GPR[rs]<<1, GPR[rt], 'Load')
GPR[rd] = read_memory_at_va(va, nbytes=2)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LHX rd, rs(rt)

Purpose:

Load Half indeXed. Load signed halfword to register $rd from memory address $rt + $rs(register plus register).

Availability:

nanoMIPS

Format:

Operation:

va = effective_address(GPR[rs], GPR[rt], 'Load')
data = read_memory_at_va(va, nbytes=2)
GPR[rd] = sign_extend(data, from_nbits=16)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LHXS rd, rs(rt)

Purpose:

Load Half indeXed Scaled. Load signed halfword to register $rd from memory address $rt+ 2*$rs (register plus scaled register).

Availability:

nanoMIPS

Format:

Operation:

va = effective_address(GPR[rs]<<1, GPR[rt], 'Load')
data = read_memory_at_va(va, nbytes=2)
GPR[rd] = sign_extend(data, from_nbits=16)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LI rt, s

Purpose:

Load Immediate. Load immediate value s to register $rt.

Availability:

nanoMIPS, availability varies by format.

Format:

LI[16]

rt = decode_gpr(rt3, 'gpr3')
s = -1 if eu == 127 else eu
not_in_nms = False

LI[48], not available in NMS

s = sign_extend(s[31:16] @ s[15:0])
not_in_nms = True

Operation:

if not_in_nms and C0.Config5.NMS == 1:
    raise exception('RI')
GPR[rt] = s

Exceptions:

Reserved Instruction for LI[48] format on NMS cores.

Assembly:

LL    rt, offset(rs)

LLE   rt, offset(rs)

LLWP  rt, ru, (rs)

LLWPE rt, ru, (rs)

Purpose:

Load Linked word/Load Linked word using EVA addressing/Load Linked Word Pair/LoadLinked Word Pair using EVA addressing. For LL/LLE,load word for atomic RMW to register $rt from address $rs + offset (register plus immediate).For LLWP/LLWPE,load words for atomic RMW to

registers $rt and $ru from address $rs. For LLE/LLWPE, translate the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS, availability varies by format.

Format:

LL

offset = sign_extend(s, from_nbits=9)
nbytes = 4
is_eva = False

LLE, present when Config5.EVA=1, requires CP0 privilege.

offset = sign_extend(s, from_nbits=9)
nbytes = 4
is_eva = True

LLWP, required (optional on NMS cores).

offset = 0
nbytes = 8
is_eva = False

LLWPE, present when Config5.EVA=1. Requires CP0 privilege.

offset = 0
nbytes = 8
is_eva = True

Operation:

if nbytes == 8 and C0.Config5.XNP:
    raise exception('RI', 'LLWP[E] requires word-paired support')
if is_eva and not C0.Config5.EVA:
    raise exception('RI')
va = effective_address(GPR[rs], offset, 'Load', eva=is_eva)
# Linked access must be aligned.
if va & (nbytes-1):
    raise exception('ADEL', badva=va)
pa, cca = va2pa(va, 'Load', eva=is_eva)
if (cca == 2 or cca == 7) and not C0.Config5.ULS:
    raise UNPREDICTABLE('uncached CCAnotsynchronizable when Config5.ULS=0')
    # (Preferred behavior for non-synchronizableaddressisBusError).
# Indicate that there is an active RMW sequence onthisprocessor.
C0.LLAddr.LLB = 1
# Save target address of active RMW sequence.
record_linked_address(va, pa, cca, nbytes=nbytes)
data = read_memory(va, pa, cca, nbytes=nbytes)
if nbytes == 4: # LL/LLE
    GPR[rt] = sign_extend(data, from_nbits=32)
else:  # LLWP/LLWPE
    word0 = data[63:32] if C0.Config.BE else data[31:0]
    word1 = data[31:0] if C0.Config.BE else data[63:32]
    if rt == ru:
        raise UNPREDICTABLE()
    GPR[rt] = sign_extend(word0, from_nbits=32)
    GPR[ru] = sign_extend(word1, from_nbits=32)

The LL/LLE/LLWP/LLWPE instructions are used to initiate an atomic read-modify-write sequence. C0.LLAddr.LLB is set to 1,indicating that there is an active RMW sequence on the current processor,

and an implementation dependent set of state is saved which indicates the address and access type of the active RMW sequence. There can be only one active RMW sequence per processor.

The RMW sequence will be completed by a matching SC/SCE/SCWP/SCWPE instruction.The storeconditional instruction will only complete if the system can guarantee that the accessed memory location has not been modified since the load-linked instruction occurred, as discussed in more detail

in

the SC/SCE/SCWP/SCWPE instruction description.

The address and CCA targeted by the LL/LLE/LLWP/LLWPE must be must be synchronizable by all processors and I/O devices sharing the location; if it is not, the result is UNPREDICTABLE. Which storage is

synchronizable is a function of both CPU and system implementations - see the SC/SCE/SCWP/SCWPE

instruction for the formal definition.The preferred behavior for a load-linked instruction which attempts to access an address which is not synchronizable is a Bus Error exception.

If Config5.ULS is set, then the system supports uncached load-linked/store-conditional accesses. Otherwise, the result of uncached accesses is unpredictable.

A LL/LLE/LLWP/LLWPE instruction on one processor must nottake action that, by itself, causes a

store-conditional instruction for the same block on another processor to fail. For example, if an implementation depends on retaining the data in the cache during the RMW sequence, cache misses caused

by a load-linked instruction must not fetch data in the exclusive state, since that would remove it from another core’s cache if it were present.

An execution of a load-linked instruction does not have to be followed by execution of store-conditional instruction; a program is free to abandon the RMW sequence without attempting a write.

Supportfor the paired word instructions LLWP/LLWPE is indicated by the Config5.XNP bit.Paired word support is required for nanoMIPS™ cores, except for NMS cores, where it is optional.

The result of LLWP/LLWPE is unpredictable if $rt and $ru are the same register.

Exceptions:

Address Error. Bus Error. Coprocessor Unusable for LLE/LLWPE. Reserved Instruction for LLE/LLWPE if EVA not implemented. Reserved Instruction for LLWP/LLWPE ifload linked pair not implemented.

TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LSA rd, rs, rt, u2

Purpose:

Load Scaled Address. Add register $rs scaled by a left shift u2 to register $rt and place the32 bit result in register $rd.

Availability:

nanoMIPS

Format:

Operation:

sum = (GPR[rs] << u2) + GPR[rt]
GPR[rd] = sign_extend(sum, from_nbits=32)

In nanoMIPS™,the shift field directly encodes the shift amount, meaning thatthe supported shift values are in the range 0 to 3 (instead of 1 to 4 in MIPSR6™).

Exceptions:

None.

Assembly:

LUI rt, %hi(imm)

Purpose:

Load Upper Immediate.Load upper 20 bits ofimmediate value imm to upper 20 bits of

register $rt, and set the lower 12 bits to zero.

Availability:

nanoMIPS

Format:

imm = sign_extend(s, from_nbits=32)

Operation:

GPR[rt] = imm

For backwards compatibility, instances of LUI which use a literal value for the immediate will be treated as containing a 16 bit immediate which should be loaded into the upper 16 bits of the target register.

To access the upper 20 bits of the register, the ’%hi(imm)’ form of the immediate must be used.

Exceptions:

None.

Assembly:

LW rt, offset(rs)

Purpose:

Load Word. Load word to register $rt from memory address $rs + offset (register plusimmediate).

Availability:

nanoMIPS, availability varies by format.

Format:

LW[U12]

offset = u

LW[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
offset = u

LW[4X4], not available in NMS

if C0.Config5.NMS == 1:
    raise exception('RI')
rt = decode_gpr(rt4[3] @ rt4[2:0], 'gpr4')
rs = decode_gpr(rs4[3] @ rs4[2:0], 'gpr4')
offset = u

LW[GP16]

rt = decode_gpr(rt3, 'gpr3')
rs = 28
offset = u

LW[GP]

rs = 28
offset = u

LW[S9]

offset = sign_extend(s, from_nbits=9)

LW[SP]

rs = 29
offset = u

Operation:

va = effective_address(GPR[rs], offset, 'Load')
data = read_memory_at_va(va, nbytes=4)
GPR[rt] = sign_extend(data, from_nbits=32)

Exceptions:

Address Error. Bus Error. Reserved Instruction for LW[4X4] format on NMS cores. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LWE rt, offset(rs)

Purpose:

Load Word using EVA addressing.

Load word to register $rt from virtual address $rs +

offset,translating the virtual address as though the core is in user mode, although it is actually in
 kernel mode.

Availability:

nanoMIPS. Optional, present when Config5.EVA=1. Requires CP0 privilege.

Format:

Operation:

offset = sign_extend(s, from_nbits=9)
if not C0.Config5.EVA:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=True)
data = read_memory_at_va(va, nbytes=4, eva=True)
GPR[rt] = sign_extend(data, from_nbits=32)

Exceptions:

Address Error. Bus Error. Coprocessor unusable. Reserved Instruction if EVA not implemented. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LWM rt, offset(rs), count

Purpose:

Load Word Multiple. Load count words of data to registers $rt, $(rt+1),

..., $(rt+count-1)

from consecutive memory address starting at $rs + offset (register plus immediate).

Availability:

nanoMIPS, not available in NMS

Format:

offset = sign_extend(s, from_nbits=9)
count = 8 if count3 == 0 else count3

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
i = 0
while i != count:
    this_rt = ( rt + i      if rt + i < 32 else
                rt + i - 16                    )
    this_offset = offset + (i<<2)
    va = effective_address(GPR[rs], this_offset, 'Load')
    data = read_memory_at_va(va, nbytes=4)
    GPR[this_rt] = sign_extend(data, from_nbits=32)
    if this_rt == rs and i != count - 1:
        raise UNPREDICTABLE()
    i += 1

LWM loads count words to sequentially numbered register from sequential memory addresses. After loading $31, the sequence of registers continues from $16. Some example encodings of the register

list are:

• rt=15, count=3:

loads [$15, $16, $17]

• rt=31, count=3:

loads [$31, $16, $17].

The result is unpredictable if an LWM instruction updates the base register prior to the final load.

LWM must be implemented in such a way as to make the instruction restartable, but the implementation does not need to be fully atomic. For instance,it is allowable for a LWM instruction to be aborted by

an exception after a subset of the register updates have occurred. To ensure restartability, any write to GPR $rs (which may be used as the final output register) must be completed atomically, that is, the

instruction must graduate if and only if that write occurs.

Exceptions:

Address Error. Bus Error. Reserved Instruction on NMS cores. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LWPC rt, address

Purpose:

Load Word PC relative. Load word to register $rt from PC relative address address.

Availability:

nanoMIPS, not available in NMS

Format:

LWPC[48]

offset = sign_extend(s, from_nbits=32)

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
address = effective_address(CPU.next_pc, offset)
data = read_memory_at_va(address, nbytes=4)
GPR[rt] = sign_extend(data, from_nbits=32)

Exceptions:

Address Error. Bus Error. Reserved Instruction on NMS cores TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LWX rd, rs(rt)

Purpose:

Load Word indeXed. Load word to register $rd from memory address $rt + $rs (registerplus register).

Availability:

nanoMIPS

Format:

Operation:

va = effective_address(GPR[rs], GPR[rt], 'Load')
data = read_memory_at_va(va, nbytes=4)
GPR[rd] = sign_extend(data, from_nbits=32)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

LWXS rd, rs(rt)

Purpose:

Load Word indeXed Scaled. Load word to register $rd from memory address

$rt + 4*$rs

(register plus scaled register).

Availability:

nanoMIPS

Format:

LWXS[32]

LWXS[16]

rd = decode_gpr(rd3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
rt = decode_gpr(rt3, 'gpr3')

Operation:

va = effective_address(GPR[rs]<<2, GPR[rt], 'Load')
data = read_memory_at_va(va, nbytes=4)
GPR[rd] = sign_extend(data, from_nbits=32)

Exceptions:

Address Error. Bus Error. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

MFC0 rt, c0s, sel

Purpose:

Move From Coprocessor 0. Write value of CP0 register indexed by c0s, sel to register $rt.

Availability:

nanoMIPS. Requires CP0 privilege.

Format:

Operation:

if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
value = read_cp0_register(c0s, sel)
GPR[rt] = sign_extend(value, from_nbits=32)

An MFC0 which targets a register which is not used on the current core will return zero.

Exceptions:

Coprocessor Unusable.

Assembly:

MFHC0 rt, c0s, sel

Purpose:

Move From High Coprocessor 0. Write bits 63..32 (when present) of CP0 register indexedby c0s, sel to register $rt.

Availability:

nanoMIPS, required.

(Optional on NMS cores). Requires CP0 privilege.

Format:

Operation:

if C0.Config5.MVH == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
value = read_cp0_register(c0s, sel, h=True)
GPR[rt] = sign_extend(value, from_nbits=32)

For certain core configurations, specific nanoMIPS32™ CP0 registers may be extended to be 64 bits wide. The MFHC0 instruction is used to read the upper 32 bits of such registers. An MFHC0 which

targets a register for which the ’high’ bits are not used will return zero.

This instruction is available when Config5.MVH=1, which is required on nanoMIPS™ cores, except for NMS cores where it is optional.

Exceptions:

Coprocessor Unusable. Reserved Instruction on NMS cores without MVH support.

Assembly:

MOD rd, rs, rt

Purpose:

Modulo. Compute signed division of register $rs by register $rt, and place the remainderin register $rd.

Availability:

nanoMIPS

Format:

Operation:

numerator = GPR[rs]
denominator = GPR[rt]
if denominator == 0:
    quotient, remainder = (UNKNOWN, UNKNOWN)
else:
    quotient, remainder = divide_integers(numerator, denominator)
GPR[rd] = sign_extend(remainder, from_nbits=32)

Exceptions:

None.

Assembly:

MODU rd, rs, rt

Purpose:

Modulo Unsigned. Compute unsigned division of register $rs by register $rt, and place theremainder in register $rd.

Availability:

nanoMIPS

Format:

Operation:

numerator = zero_extend(GPR[rs], from_nbits=32)
denominator = zero_extend(GPR[rt], from_nbits=32)
if denominator == 0:
    quotient, remainder = (UNKNOWN, UNKNOWN)
else:
    quotient, remainder = divide_integers(numerator, denominator)
GPR[rd] = sign_extend(remainder, from_nbits=32)

Exceptions:

None.

Assembly:

MOVE.BALC rd, rt, address

Purpose:

Move and Branch and Link, Compact. Copy value of register $rt to register $rd, and performan unconditional PC relative branch to address, placing the return address in register $31.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
rd = decode_gpr(rd1, 'gpr1')
rt = decode_gpr(rtz4[3] @ rtz4[2:0], 'gpr4.zero')
offset = sign_extend(s, from_nbits=22)
address = effective_address(CPU.next_pc, offset)
GPR[rd] = GPR[rt]
GPR[31] = CPU.next_pc
CPU.next_pc = address

Although this instruction is called MOVE.BALC, the order of the updates to PC, $31 and $rd is invisible to software, and an implementation may choose any order for carring out these steps.

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

MOVE rt, rs

Purpose:

Move. Copy value of register $rs to register $rt.

Availability:

nanoMIPS

Format:

Operation:

GPR[rt] = GPR[rs]

Exceptions:

None.

Assembly:

MOVEP dst1, dst2, src1, src2

Purpose:

Move Pair. Copy value of register $src1 to register $dst1, and copy value of register $src2to register $dst2.

Availability:

nanoMIPS, not available in NMS

Format:

MOVEP

dst1 = decode_gpr(rd2[1] @ rd2[0], 'gpr2.reg1')
dst2 = decode_gpr(rd2[1] @ rd2[0], 'gpr2.reg2')
src1 = decode_gpr(rsz4[3] @ rsz4[2:0], 'gpr4.zero')
src2 = decode_gpr(rtz4[3] @ rtz4[2:0], 'gpr4.zero')

MOVEP[REV]

dst1 = decode_gpr(rs4[3] @ rs4[2:0], 'gpr4')
dst2 = decode_gpr(rt4[3] @ rt4[2:0], 'gpr4')
src1 = decode_gpr(rd2[1] @ rd2[0], 'gpr2.reg1')
src2 = decode_gpr(rd2[1] @ rd2[0], 'gpr2.reg2')

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
if dst1 == src1 or dst1 == src2 or dst2 == src1 or dst2 == src2:
    GPR[dst1] = UNKNOWN
    GPR[dst2] = UNKNOWN
else:
    GPR[dst1] = GPR[src1]
    GPR[dst2] = GPR[src2]

The output register values are unpredictable if either of the output registers is also used as an input.

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

MOVN rd, rs, rt

Purpose:

Move if Not zero. Copy value of register $rs to register $rd if register $rt is not zero.

Availability:

nanoMIPS

Format:

Operation:

GPR[rd] = GPR[rs] if GPR[rt] != 0 else GPR[rd]

Exceptions:

None.

Assembly:

MOVZ rd, rs, rt

Purpose:

Move if Zero. Copy value of register $rs to register $rd if register $rt is zero.

Availability:

nanoMIPS

Format:

Operation:

GPR[rd] = GPR[rs] if GPR[rt] == 0 else GPR[rd]

Exceptions:

None.

Assembly:

MTC0 rt, c0s, sel

Purpose:

Move To Coprocessor 0. Write value of register $rt to CP0 register indexed by c0s, sel.

Availability:

nanoMIPS. Requires CP0 privilege.

Format:

Operation:

if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
write_cp0_register(GPR[rt], c0s, sel)

An MTC0 to a register which is not used on the current core is ignored.

When a register is extended to have high bits for a specific configuration (see MTHC0), legacy software which is not aware of the existence of these high bits still needs to function correctly.In such cases,

the architecture may require that an MTC0 modifies the high 32 bits of the register as well as the low 32 bits to give the correct legacy behavior.

For this reason, when setting an extended CP0 register, the MTC0 to set the low 32 bits should always precede the MTHC0 to set the high 32 bits. Also, a read-modify-write sequence to set a specific bitfield

in the low 32 bits should read both the low 32 and high 32 bits, then do MTC0 followed by MTHC0 to write the modified value back.

Exceptions:

Coprocessor Unusable.

Assembly:

MTHC0 rt, c0s, sel

Purpose:

Move To High Coprocessor 0. Write value of register $rt to bits 63..32 (when present) ofCP0 register indexed by c0s, sel.

Availability:

nanoMIPS, required.

(Optional on NMS cores). Requires CP0 privilege.

Format:

Operation:

if C0.Config5.MVH == 0:
    raise exception('RI')
if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
write_cp0_register(GPR[rt], c0s, sel, h=True)

For certain core configurations, specific nanoMIPS32™ CP0 registers may be extended to be 64 bits wide.The MTHC0 instruction is used to write the upper 32 bits of such registers. An MTHC0 to a

register for which the ’high’ bits are not used will be ignored.

When a register is extended to have high bits for a specific configuration, legacy software which is not aware of the existence of these high bits still needs to function correctly.In such cases, the architecture

may require that an MTC0 modifies the high 32 bits of the register as well as the low 32 bits to give the correct legacy behavior.

For this reason, when setting an extended CP0 register, the MTC0 to set the low 32 bits should always precede the MTHC0 to set the high 32 bits. Also, a read-modify-write sequence to set a specific bitfield

in the low 32 bits should read both the low 32 and high 32 bits, then do MTC0 followed by MTHC0 to write the modified value back.

This instruction is available when Config5.MVH=1, which is required on nanoMIPS™ cores, except for NMS cores where it is optional.

Exceptions:

Coprocessor Unusable. Reserved Instruction on NMS cores without MVHm support.

Assembly:

MUH rd, rs, rt

Purpose:

Multiply High. Multiply signed word values from registers $rs and $rt, and place bits 63..32of the result in register $rd.

Availability:

nanoMIPS

Format:

Operation:

result = GPR[rs] * GPR[rt]
result_hi = result[63:32]
GPR[rd] = sign_extend(result_hi, from_nbits=32)

Exceptions:

None.

Assembly:

MUHU rd, rs, rt

Purpose:

Multiply High Unsigned. Multiply unsigned word values in registers $rs and $rt, and placebits 63..32 of the result in register $rd.

Availability:

nanoMIPS

Format:

Operation:

rs_unsigned = zero_extend(GPR[rs], from_nbits=32)
rt_unsigned = zero_extend(GPR[rt], from_nbits=32)
result = rs_unsigned * rt_unsigned
result_hi = result[63:32]
GPR[rd] = sign_extend(result_hi, from_nbits=32)

Exceptions:

None.

Assembly:

MUL dst, src1, src2

Purpose:

Multiply. Multiply signed word values in registers $src1 and $src2, and place bits 31..0 ofthe result in register $dst.

Availability:

nanoMIPS, availability varies by format.

Format:

MUL[32]

dst = rd
src1 = rs
src2 = rt
not_in_mms = False

MUL[4X4], not available in NMS

dst = decode_gpr(rt4, 'gpr4')
src1 = decode_gpr(rt4, 'gpr4')
src2 = decode_gpr(rs4, 'gpr4')
not_in_mms = True

Operation:

if not_in_mms and C0.Config5.NMS == 1:
    raise exception('RI')
result = GPR[src1] * GPR[src2]
GPR[dst] = sign_extend(result, from_nbits=32)

Exceptions:

Reserved Instruction for MUL[4X4] format on NMS cores.

Assembly:

MULU rd, rs, rt

Purpose:

Multiply Unsigned. Multiply unsigned word values in registers $rs and $rt, and place bits31..0 of the result in register $rd.

Availability:

nanoMIPS

Format:

Operation:

rs_unsigned = zero_extend(GPR[rs], from_nbits=32)
rt_unsigned = zero_extend(GPR[rt], from_nbits=32)
result = rs_unsigned * rt_unsigned
GPR[rd] = sign_extend(result, from_nbits=32)

Exceptions:

None.

Assembly:

NOP

Purpose:

No Operation.

Availability:

nanoMIPS

Format:

NOP[32]

NOP[16]

Operation:

# No operation pass

The NOP[32] encoding is equivalent to an SLL[32] instruction using $0 as output and a shift value of 0. The NOP[16] encoding is equivalent to an ADDIU[RS5] instruction using $0 as output. Therefore NOP

does not necessarily need any additionalimplementation in hardware beyond the normal behavior of the SLL[32] and ADDIU[RS5] instructions.

If software intentionally generates a NOP instruction, it should only generate these specific encodings, rather than other instructions writing to $0 which would also result in no operation.

If hardware implements a performance counter for nops,it can expect these specific instruction encodings to be used.

It should ignore the x field of the encoding, treating all values of x as representing

a valid NOP instruction. Software on the other hand should only generate NOP instructions with an x value of 0.

As for all instruction definitions containing x fields, this methodology allows for the possibility that the meaning of x values other than zero might be enhanced in the future, with the understanding that cores

prior to the enhanced definition will treat the x!=0 encodings as equivalent to the x==0 instruction.

Exceptions:

None.

Assembly:

NOR rd, rs, rt

Purpose:

NOR. Compute logical NOR of registers $rs and $rt, placing the result in register $rt.

Availability:

nanoMIPS

Format:

Operation:

GPR[rd] = ~(GPR[rs] | GPR[rt])

Exceptions:

None.

Assembly:

NOT rt, rs

Purpose:

NOT. Write logical inversion of register $rs to register $rt.

Availability:

nanoMIPS

Format:

Operation:

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
GPR[rt] = ~GPR[rs]

Exceptions:

None.

Assembly:

OR rd, rs, rt

Purpose:

OR. Compute logical OR of registers $rs and $rt, placing the result in register $rt.

Availability:

nanoMIPS

Format:

OR[32]

OR[16]

rt = decode_gpr(rt3, 'gpr3')
rs = decode_gpr(rs3, 'gpr3')
rd = rt

Operation:

GPR[rd] = GPR[rs] | GPR[rt]

Exceptions:

None.

Assembly:

ORI rt, rs, u

Purpose:

OR Immediate. Compute logical OR of register $rs with immediate u, placing the result inregister $rt.

Availability:

nanoMIPS

Format:

Operation:

GPR[rt] = GPR[rs] | u

Exceptions:

None.

Assembly:

PAUSE

Purpose:

Pause. Pause until LL Bit is cleared.

Availability:

nanoMIPS

Format:

Operation:

if C0.LLAddr.LLB:
    CPU.in_pause_state = True

The purpose ofthe PAUSE instruction is halt a thread (rather than entering a spin loop) when itis waiting to acquire an LL/SC lock. This is particularly useful on multi-threaded processors, since the

waiting thread may be using the same instruction pipeline as the thread which currently owns the lock, and hence entering a spin loop will delay the other thread from completing its task and freeing the

lock.

When a thread is in the paused state,it should not issue any instructions. The paused state will be

cleared either if the LLBit for the thread gets cleared, or if the thread takes an interrupt.If an interrupt occurs,

it is implementation dependent whether C0.EPC points to the PAUSE instruction or the

instruction after the PAUSE.

In LL/SC lock software, the LLBit of the waiting thread will always be cleared when the thread which owns the lock does a store instruction to the lock address in order to clear the lock. Thus the paused

thread will always be woken when it has another opportunity to acquire the lock. After the PAUSE instruction completes, software is expected to attempt to acquire the lock again by re-executing the

LL/SC sequence.

It is legal to implement PAUSE as a NOP instruction.In this case, the behavior of LL/SC lock software will be equivalent to executing a spin loop to acquire the lock. Software using PAUSE will still work,

but the benefit of having the waiting thread not consume instruction issue slots will be lost.

PAUSE is encoded as an SLL instruction with a shift value of 5, targeting GPR $0. Hence PAUSE will behave as a NOP instruction if no additional behavior beyond that of SLL is implemented.

The following assembly code example shows how the PAUSE instruction can be used to halt a thread while it is waiting to acquire an LL/SC lock.

acquire_lock:
        ll      t0, 0(a0)    /* Read softwarelock, set LLBit. */
        bnezc  t0, acquire_lock_retry /* Branch if softwarelock is taken.*/
        addiu   t0, t0, 1    /* Set the software lock. */
        sc      t0, 0(a0)    /* Try to store the softwarelock. */
        bnezc  t0, 10f      /* Branchiflockacquired successfully.*/
        sync
acquire_lock_retry:
        pause                /* Wait for LLBITtoclear before retrying. */
        bc      acquire_lock /* Now retrytheoperation. */
10:
        /* Critical Region Code */
        ...
release_lock:
        sync
        sw      zero, 0(a0)  /* Releasesoftwarelock,clearing LLBIT
                                for any PAUSEd waiters */

Exceptions:

None.

Assembly:

PREF hint, offset(rs)

PREFE hint, offset(rs)

Purpose:

Prefetch/Prefetch using EVA addressing. Perform a prefetch operation of type hint at address $rs + offset (register plus immediate). For PREFE, translate the virtual address as though the core is in user mode, although it is actually in kernel mode.

Availability:

nanoMIPS, availability varies by format.

Format:

PREF[S9]

offset = sign_extend(s, from_nbits=9)
is_eva = False

PREF[U12]

offset = u
is_eva = False

PREFE, present when Config5.EVA=1, requires CP0 privilege.

312625212016151411109870

with hint!=31

offset = sign_extend(s, from_nbits=9)
is_eva = True

Operation:

if is_eva and not C0.Config5.EVA:
    raise exception('RI')
if is_eva and not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
va = effective_address(GPR[rs], offset, 'Load', eva=is_eva)
# Perform implementation dependent prefetch actions
pref(va, hint, eva=is_eva)

The PREF and PREFE instructions request that the processor take some action to improve program performance in accordance with the intended data usage specified by the hint argument.This is

typically done by moving data to or from the cache at the specified address. The meanings of hint are as follows:

•      hint=0:
  

load

–

Use: Prefetched data is expected to be read (not modified).

–

Action: Fetch data as if for a load.

• hint=1: store
  

–

Use: Prefetched data is expected to be stored or modified.

–

Action: Fetch data as if for a store.

• hint=2: L1 LRU hint
  

–

Mark the line as LRU in the L1 cache and thus preferred for next eviction.

Implementations can choose to writeback and/or invalidate the line as long as no architectural state is

modified.

• hint=3: Reserved for Implementation
  

• hint=4:
  

load_streamed

–

Use: Prefetched data is expected to be read (not modified) but not reused extensively;

it

”streams” through cache.

–

Action: Fetch data as if for a load and place it in the cache so that it does not displace data

prefetched as ”retained”.

• hint=5: store_streamed
  

–

Use: Prefetched data is expected to be stored or modified but not reused extensively;

it

”streams” through cache.

–

Action: Fetch data as if for a store and place it in the cache so that it does not displace data

prefetched as ”retained”.

• hint=6:
  

load_retained

–

Use: Prefetched data is expected to be read (not modified) and reused extensively; it should

be ”retained” in the cache.

–

Action: Fetch data as if for a load and place it in the cache so that it is not displaced by data

prefetched as ”streamed”.

• hint=7: store_retained
  

–

Use: Prefetched data is expected to be stored or modified and reused extensively; it should

be ”retained” in the cache.

–

Action: Fetch data as if

for a store and place it in the cache so that it is not displaced by

data prefetched as ”streamed”.

• hint=8..15: L2 operation
  

–

In the Release 6 architecture, hint codes 8..15 are treated the same as hint codes 0..7 respectively, but operate on the L2 cache.

• hint=16..23: L3 operation
  

–

In the Release 6 architecture, hint codes 16..23 are treated the same as hint codes 0..7 respectively, but operate on the L3 cache.

• hint=24..30: Reserved for Architecture
  

–

These hint codes are reserved in nanoMIPS and should act as a NOP. (This is not the same

as the MIPSR6 behavior, where these hints give a Reserved Instruction exception). Note that hint=31 is not listed as that encoding is decoded as a SYNCI instruction.

The action taken for a specific PREF instruction is both system and context dependent. Any action, including doing nothing, is permitted as long as it does not change architecturally visible state or alter

the meaning of a program.

PREF does not cause addressing-related exceptions, including TLB exceptions.If the address specified would cause an addressing exception, the exception condition is ignored and no data movement occurs.

For cached addresses, the expected and useful action is for the processor to prefetch a block of data that includes the effective address. The size of the block and the level of the memory hierarchy it is

fetched into are implementation specific.

PREF neither generates a memory operation nor modifies the state of a cache line for addresses with an uncached CCA.

Prefetch operations have no effect on cache lines that were previously locked with the CACHE instruction.

In coherent multiprocessor implementations,if the effective address uses a coherent CCA, then the instruction causes a coherent memory transaction to occur.This means a prefetch issued on one

processor can cause data to be evicted from the cache in another processor.

The memory transactions which occur as a result of a PREF instruction, such as cache refill or cache writeback, obey the same ordering and completion rules as other load or store instructions.

It is implementation dependent whether a Bus Error or Cache Error exception is reported if such an error is detected as a byproduct ofthe action taken by the PREF instruction.Implementations are

encouraged to report such errors only if there is a specific requirement for high-reliability. Note that

suppressing a bus or cache error in this case may require that the processor communicate to the system that the reference is speculative.

Hint field encodings whose function is described as ”streamed” or ”retained” convey usage intent from software to hardware. Software should not assume that hardware will always prefetch data in an

optimal way.If data is to be truly retained, software should use the Cache instruction to lock data into the cache.

Itis implementation dependent whether a data watch or EJTAG breakpoint exception is triggered by a prefetch instruction whose address matches the Watch register address match or EJTAG data

breakpoint conditions. The preferred implementation is not to match on the prefetch instruction.

Exceptions:

Bus Error. Cache Error. Coprocessor Unusable for PREFE. Reserved Instruction for PREFE if EVA not implemented.

Assembly:

RDHWR rt, hs, sel

Purpose:

Read Hardware Register. Read specific CP0 privileged state (identified by hs, sel) to register$rs. Kernel code can enable or disable user mode RDHWR accesses by programming the enable bits in the HWREna register.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS == 1:
    raise exception('RI')
if not IsCoprocessor0Enabled():
   if not C0.HWREna & (1 << hs):
       raise exception('RI', 'Required HWREnabitnotset')
if sel and hs != 4:
    raise exception('RI', 'sel fieldnot supported for this hs')
if is_guest_mode():
    check_gpsi('CP0')
if hs == 0:
    GPR[rt] = C0.EBase.CPUNum
elif hs == 1:
    GPR[rt] = synci_step()
elif hs == 2:
    if is_guest_mode():
        check_gpsi('GT')
        GPR[rt] = guest_count()
    else:
        GPR[rt] = C0.Count
elif hs == 3:
    GPR[rt] = CPU.count_resolution
elif hs == 4:
    if not C0.Config1.PC:
        raise exception('RI', 'Perf Counters not implemented')
    GPR[rt] = read_cp0_register(25, sel)  # Performance counter register
elif hs == 5:
    GPR[rt] = C0.Config5.XNP
elif hs == 29:
    if not C0.Config3.ULRI:
        raise exception('RI')
    GPR[rt] = sign_extend(C0.UserLocal)
else:
    raise exception('RI')

Exceptions:

Coprocessor Unusable. Reserved Instruction for unsupported register numbers. Reserved Instruction on NMS cores.

Assembly:

RDPGPR rt, rs

Purpose:

Read Previous GPR. Write the value of register $rs from the previous shadow register set(SRSCtl.PSS) to register $rt in the current shadow register set (SRSCtl.CSS). If shadow register sets are not implemented,just copy the value from register $rs to register $rt.

Availability:

nanoMIPS. Requires CP0 privilege.

Format:

Operation:

if not IsCoprocessor0Enabled():
    raise coprocessor_exception(0)
if C0.SRSCtl.HSS > 0:
    GPR[rt] = SRS[C0.SRSCtl.PSS][rs]
else:
    GPR[rt] = GPR[rs]

Exceptions:

Coprocessor Unusable.

Assembly:

RESTORE     u[, dst1 [, dst2 [, ...]]] # jr=0 implied

RESTORE.JRC u[, dst1 [, dst2 [, ...]]]  # jr=1 implied

Purpose:

Restore callee saved registers/Restore callee saved registers and Jump to Return address,Compact. Restore registers dst1, [dst2,...]from addresses at the top of the local stack frame ($29 +

u - 4, $29 + u - 8, ...), then point register $29 back to the caller’s stack frame by adding offset u. For RESTORE.JRC, return from the current subroutine by jumping to the address in $31.

Availability:

nanoMIPS, availability varies by format.

Format:

RESTORE[32]

jr = 0

RESTORE.JRC[16]

rt = 30 if rt1 == 0 else 31
gp = 0
jr = 1

RESTORE.JRC[32], gp case not available in NMS

jr = 1

Operation:

if gp and C0.Config5.NMS:
    raise exception('RI')
i = 0
while i != count:
    this_rt = ( 28          if gp and (i + 1 == count) else
                rt + i      if rt + i < 32             else
                rt + i - 16                                 )
    this_offset = u - ( (i+1) << 2 )
    va = effective_address(GPR[29], this_offset, 'Load')
    if va & 3:
        raise exception('ADEL', badva=va)
    data = read_memory_at_va(va, nbytes=4)
    GPR[this_rt] = sign_extend(data, from_nbits=32)
    if this_rt == 29:
        raise UNPREDICTABLE()
    i += 1
GPR[29] = effective_address(GPR[29], u)
if jr:
    CPU.next_pc = GPR[31]

The purpose of the RESTORE and RESTORE.JRC instructions is to restore callee saved registers from the stack on exit from a subroutine, adjust the stack pointer register $29 to point to the caller’s stack

frame, and for RESTORE.JRC to return from the subroutine by jumping to the address in register $31. RESTORE/RESTORE.JRC will usually be paired with a matching SAVE instruction at the start of the

subroutine, and SAVE and RESTORE take the same arguments.

The arguments for RESTORE/RESTORE.JRC consist of the amount to increment the stack by, and a list of registers to restore from to the stack. The increment is a double word aligned immediate value u

in the range 0 to 4092. The register list can contain up to 16 consecutive registers. The count of the number of registers is encoded in the instruction’s count field. The first register in the list is encoded

in the rt field of the instruction.

The register list is allowed to wrap around from register $31 back to register $16 and still be considered consecutive; this allows fp ($30) and ra ($31) and the saved temporary registers s0-s7 ($16 - $23) to

be restored in one instruction.

Additionally, $28 (the global pointer register) will be used in place of last register in the sequence if the ’gp’ bit in the instruction encoding is set. This feature (which is not available for NMS cores) makes it

possible to treat $28 as a callee saved register for environments such as Linux which require it.

The restored registers are read from memory addresses $29+ u -4, $29 + u -8, $29 + u -12,... etc,i.e. at the top of the local stack frame. The stack pointer is then adjusted by adding the size u of

the local stack frame, so that it points back to the caller’s stack frame.

RESTORE.JRC with count=0 adjusts the stack pointer and jumps to the address in $31, but does not restore any registers from memory.Thus the RESTORE.JRC[16]instruction format can be used to

provide ADDIU $29, $29,u; JRC $31 behavior using a single 16 bit instruction.

The result of a RESTORE instruction is UNPREDICTABLE if the register list includes register $29.

RESTORE/RESTORE.JRC must be implemented in such a way as to make the instructions restartable,

butthe implementation does not need to be fully atomic.Forinstance,itis allowable for a RESTORE/RESTORE.JRC instruction to be aborted by an exception after a subset of the register updates

have occurred. To ensure restartability, the write to GPR $29 and the jump (for RESTORE.JRC) must be completed atomically, that is, the instruction must graduate if and only if those writes occur.

Exceptions:

Address Error. Bus Error. Reserved Instruction for gp=1 cases on NMS cores. TLB Invalid. TLB Read Inhibit. TLB Refill. Watch.

Assembly:

ROTR rt, rs, shift

Purpose:

Rotate Right. Rotate the word value in register $rs by shift value shift, and place the resultin register $rt.

Availability:

nanoMIPS

Format:

Operation:

tmp = GPR[rs][31:0] @ GPR[rs][31:0]
result = tmp >> shift
GPR[rt] = sign_extend(result, from_nbits=32)

Exceptions:

None.

Assembly:

ROTRV rd, rs, rt

Purpose:

Rotate Right Variable. Rotate the word value in register $rs by the shift value contained inregister $rt, and place the result in register $rd.

Availability:

nanoMIPS

Format:

Operation:

shift = GPR[rt] & 0x1f
tmp = GPR[rs][31:0] @ GPR[rs][31:0]
result = tmp >> shift
GPR[rd] = sign_extend(result, from_nbits=32)

Exceptions:

None.

Assembly:

ROTX rt, rs, shift, shiftx, stripe

Purpose:

Rotate and eXchange. Rotate and exchange bits in the word value in register $rs and placeresult in register $rt. Specific choices of the shift, shiftx and stripe arguments allow this instruction to perform bit and byte reordering operations including BYTEREVW, BYTEREVH, BITREVW, BITREVH

and BITREVB.

Availability:

nanoMIPS, not available in NMS

Format:

Operation:

if C0.Config5.NMS:
    raise exception('RI')
tmp0 = GPR[rs][31:0] @ GPR[rs][31:0]
tmp1 = tmp0
for i in range(47):  # 0..46
    s = shift if (i & 0b01000) else shiftx
    if stripe and not (i & 0b00100): s = ~s
    if s[4]: tmp1[i] = tmp0[i+16]
tmp2 = tmp1
for i in range(39):  # 0..38
    s = shift if (i & 0b00100) else shiftx
    if s[3]: tmp2[i] = tmp1[i+8]
tmp3 = tmp2
for i in range(35):  # 0..34
    s = shift if (i & 0b00010) else shiftx
    if s[2]: tmp3[i] = tmp2[i+4]
tmp4 = tmp3
for i in range(33):  # 0..32
    s = shift if (i & 0b00001) else shiftx
    if s[1]: tmp4[i] = tmp3[i+2]
tmp5 = tmp4
for i in range(32):  # 0..31
    s = shift;
    if s[0]: tmp5[i] = tmp4[i+1]
GPR[rt] = sign_extend(tmp5, from_nbits=32)

The ROTX instruction can be used to reverse elements of a selected size within blocks of a different selected size. Some example use cases are shown in the table below. The ’Result’ shows the output value

assuming an input value of abcdefgh ijklmnopqrstuvwx yz012345, where each character represents the value of a single bit.

Assembly/Result from

                                                              abcdefgh ijklmnop qrstuvwx

AliasOperationyz012345

BITREVWReverse all bitsROTX rt, rs, 31, 0

                                                              543210zy xwvutsrq ponmlkji
                                                              hgfedcba

BITREVHReverse bits in halfsROTX rt, rs, 15, 16

                                                              ponmlkji hgfedcba 543210zy
                                                              xwvutsrq

BITREVBReverse bits in bytesROTX rt, rs, 7, 8, 1

                                                              hgfedcba ponmlkji xwvutsrq
                                                              543210zy

BYTEREVWReverse all bytesROTX rt, rs, 24, 8

                                                              yz012345 qrstuvwx ijklmnop
                                                              abcdefgh

BYTEREVHReverse bytes in halfsROTX rt, rs, 8, 24

                                                              ijklmnop abcdefgh yz012345
                                                              qrstuvwx

Reverse all nibblesROTX rt, rs, 28, 4

                                                              2345yz01 uvwxqrst mnopijkl
                                                              efghabcd

Reverse nibbles in halfsROTX rt, rs, 12, 20

                                                              mnopijkl efghabcd 2345yz01
                                                              uvwxqrst

Reverse nibbles in bytesROTX rt, rs, 4, 12, 1

                                                              efghabcd mnopijkl uvwxqrst

Assembly/Result from

                                                              abcdefgh ijklmnop qrstuvwx

AliasOperationyz012345

Reverse all bit pairsROTX rt, rs, 30, 2

                                                              452301yz wxuvstqr opmnklij
                                                              ghefcdab

Reverse pairs in halfsROTX rt, rs, 14, 18

                                                              opmnklij ghefcdab 452301yz
                                                              wxuvstqr

Reverse pairs in bytesROTX rt, rs, 6, 10, 1

                                                              ghefcdab opmnklij wxuvstqr
                                                              452301yz

Assembler aliases are provided for certain cases, as indicated in the table.

The MIPS32™ instructions BITSWAP and WSBH are equivalent to BITREVB and BYTEREVH respectively, and are also provided as assembler aliases to ROTX.

The ROTX instruction is designed to be implementable with minimal overhead using existing logic for the ROTR instruction. ROTR can be implemented using a barrel shifter, where the select signals for

the multiplexers at each stage are the bits of the ’shift’ argument. For ROTX, the mux select signals depend on the bit position as well as the stage of the shifter, and are a function of the ’shift’,’shiftx’

and ’stripe’ arguments.

Exceptions:

Reserved Instruction on NMS cores.

Assembly:

SAVE u[, src1 [, src2 [, ...]]]

Purpose:

Save callee saved registers.

Save registers src1,[src2,...]to addresses just below the

current stack pointer ($29) address and adjust the stack pointer by subtracting offset u to accommodate the saved registers and the local stack frame.

Availability:

nanoMIPS, availability varies by format.

Format:

SAVE[16]

rt = 30 if rt1 == 0 else 31
gp = 0

SAVE[32], gp case not available in NMS

Operation:

if gp and C0.Config5.NMS:
    raise exception('RI')
i = 0
while i != count:
    this_rt = ( 28          if gp and (i + 1 == count) else
                rt + i      if rt + i < 32             else
                rt + i - 16                                 )
    this_offset = - ( (i+1) << 2 )
    va = effective_address(GPR[29], this_offset, 'Load')
    if va & 3:
        raise exception('ADES', badva=va)
    data = zero_extend(GPR[this_rt], from_nbits=32)
    write_memory_at_va(data, va, nbytes=4)
    i += 1
GPR[29] = effective_address(GPR[29], -u)

The purpose of the SAVE instruction is to save callee saved registers to the stack on entry to a subroutine, and adjust the stack pointer register ($29) to accommodate the saved registers and the subroutine’s local stack frame.

The instruction specification consists of the amount to decrement the stack by, and a list of registers to save to the stack. The stack decrement is a double word aligned immediate value u in the range

0 to 4092. The register list can contain up to 16 consecutive registers. The count of the number of registers in the register list is encoded in the instruction’s count field. The first register in the list is

encoded in the rt field of the instruction.

The register list is allowed to wrap around from register $31 back to register $16 and still be considered consecutive; this allows fp ($30) and ra ($31) and the saved temporary registers s0-s7 ($16 - $23) to

be saved in one instruction.

Additionally, $28 (the global pointer register) will be used in place of last register in the sequence if the ’gp’ bit in the instruction encoding is set. This feature (which is not available for NMS cores) makes it

possible to treat $28 as a callee saved register for environments such as Linux which require it.

The saved registers are written to memory addresses $29-4, $29-8, $29-12,...etc,i.e.just below the current stack pointer address. The stack pointer is then adjusted by subtracting offset u, which

should be chosen to accommodate the saved registers and current subroutine’s local stack frame, while maintaining the required stack pointer alignment.

SAVE with count=0 adjusts the stack pointer but does not save any registers to memory.Thus the

SAVE[16] instruction format can be used to provide ADDIU16$29, $29, -u behavior.

SAVE must be implemented in such a way as to make the instruction restartable, but the implementation does not need to be fully atomic. For instance, it is allowable for a SAVE instruction to be aborted

by an exception after a subset ofthe memory updates have occurred.To ensure restartability,the write to GPR $29 must be completed atomically,that is,the instruction must graduate if and only if

that write occurs.

Exceptions:

Address Error.Bus Error.Reserved Instruction for gp=1 cases on NMS cores.TLB Invalid.TLB Modified. TLB Refill. Watch.

Assembly:

SB rt, offset(rs)

Purpose:

Store Byte.

Store byte from register $rt to memory address $rs + offset (register plus

immediate).

Availability:

nanoMIPS

Format:

SB[U12]

offset = u

SB[16]

rt = decode_gpr(rtz3, 'gpr3.src.store')
rs = decode_gpr(rs3, 'gpr3')
offset = u