Encoding:

Format:

ADDIU rx, immediate

Purpose:

Add Immediate Unsigned Word (2-Operand, Extended)

To add a constant to a 32-bit integer.

Description:

GPR[rx] = GPR[rx] + immediate

The 16-bit immediate is sign-extended and then added to the contents of GPR rx to form a 32-bit result. The result is placed in GPR rx.

No integer overfl w exception occurs under any circumstances.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)] + sign_extend(immediate)
GPR[Xlat(rx)] = temp

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer;this operation is 32-bit modulo arithmetic that does not trap on overfl w. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overfl w, such as C language arithmetic.

Encoding:

Format:

ADDIU rx, pc, immediate

Purpose:

Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)

To add a constant to the program counter.

Description:

GPR[rx] = PC + immediate

The 16-bitimmediate is sign-extended and added to the address of the ADDIU instruction. Before the addition,the two lower bits of the instruction address are cleared.

The result of the addition is placed in GPR rx.

No integer overfl w exception occurs under any circumstances.

Restrictions:

A PC-relative, extended ADDIU may not be placed in the delay slot of a jump instruction.

Operation:

temp = (PCGPRLEN-1..2 || 02) + sign_extend(immediate)
GPR[Xlat(rx)] = temp

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer;this operation is 32-bit modulo arithmetic that does not trap on overfl w. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overfl w, such as C language arithmetic.

The assembler LA (Load Address) pseudo-instruction is implemented as a PC-relative add.

Encoding:

Format:

ADDIU rx, sp, immediate

Purpose:

Add Immediate Unsigned Word (3-Operand, SP-Relative, Extended)

To add a constant to the stack pointer.

Description:

GPR[rx] = GPR[sp] + immediate

The 16-bit immediate is sign-extended and then added to the contents of GPR 29 to form a 32-bit result. The result is placed in GPR rx.

No integer overfl w exception occurs under any circumstances.

Restrictions:

None

Operation:

temp = GPR[29] + sign_extend(immediate
GPR[Xlat(rx)] = temp

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer;this operation is 32-bit modulo arithmetic that does not trap on overfl w. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overfl w, such as C language arithmetic.

Encoding:

Format:

ADDIU ry, rx, immediate

Purpose:

Add Immediate Unsigned Word (3-Operand, Extended)

To add a constant to a 32-bit integer.

Description:

GPR[ry] = GPR[rx] + immediate

The 15-bit immediate is sign-extended and then added to the contents of GPR rx to form a 32-bit result. The result is placed into GPR ry.

No integer overfl w exception occurs under any circumstances.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)] + sign_extend(immediate)
GPR[Xlat(ry)] = temp

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer;this operation is 32-bit modulo arithmetic that does not trap on overfl w. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overfl w, such as C language arithmetic.

Encoding:

Format:

ADDIU  sp, immediate

Purpose:

Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)

To add a constant to the stack pointer.

Description:

GPR[sp] = GPR[sp] + immediate

The 16-bit immediate is sign-extended, and then added to the contents of GPR 29 to form a 32-bit result. The result is placed in GPR 29.

No integer overfl w exception occurs under any circumstances.

Restrictions:

None

Operation:

temp = GPR[29] + sign_extend(immediate)
GPR[29] = temp

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer;this operation is 32-bit modulo arithmetic that does not trap on overfl w. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overfl w, such as C language arithmetic.

Encoding:

Format:

ADDU rz, rx, ry

Purpose:

Add Unsigned Word (3-Operand)

To add 32-bit integers.

Description:

GPR[rz] = GPR[rx] + GPR[ry]

The contents of GPR rxand GPR ryare added together to form a 32-bit result. The result is placed into GPR rz.

No integer overfl w exception occurs under any circumstances.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)] + GPR[Xlat(ry)]
GPR[Xlat(rz)] = temp

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer;this operation is 32-bit modulo arithmetic that does not trap on overfl w. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overfl w, such as C language arithmetic.

Encoding:

Format:

AND rx, ry

Purpose:

AND

To do a bitwise logical AND.

Description:

GPR[rx] = GPR[rx] AND GPR[ry]

The contents of GPR ry are combined with the contents of GPR rx in a bitwise logical AND operation. The result is placed in GPR rx.

Restrictions:

None

Operation:

GPR[Xlat(rx)] = GPR[Xlat(rx)] and GPR[Xlat(ry)]

Exceptions:

None

Encoding:

Format:

ASMACRO select,p0,p1,p2,p3,p4

The formatlisted is the most generic assemblerformat and is unlikely to be used for an actualimplementation of application-specifi macro instructions. Rather, the assembler format is likely to represent the use of the macro, with the assembler turning that format into the appropriate bit pattern required by the instruction.

Purpose:

Application-Specific Macro Instruction

To execute an implementation-definable macro instruction

Description:

The ASMACRO instruction is the programming interface to the implementation-definabl macro instruction facility that is defined by the MIPS16e architecture

The selectfielspecifie which of 8 possible macros is expanded. The definitioof each macro specifiehow the parameters p0, p1, p2, p3, and p4 are substituted into the 32-bit instructions with which the macro is defined The execution of the 32-bit instructions occurs while PC remains unchanged.

Itis implementation-dependent whether a processorimplements any implementation-definabl macro instructions and, if it does, how many. It is implementation-dependent whether the macro is executed with interrupts disabled.

Restrictions:

The 32-bit instructions with which the macro is define must by chosen with care. Issues of atomicity, restartability of the instruction sequence, and similar factors must be considered when using the implementation-definabl macro instruction facility. Failure to do so can cause UNPREDICTABLE behavior.

If implementation-definabl macro instructions are not implemented by the processor, or if the select fielreferences a specific macro which is not implemented by the processo , a Reserved Instruction exception is signaled.

Operation:

ExecuteMacro(sel,p0,p1,p2,p3,p4)

Exceptions:

Reserved Instruction

Others as may be generated by the 32-bit instructions included in each macro expansion.

Programming Notes:

Implementations may impose certain restrictions on 32-bitinstructions are supported within an ASMACRO instruction. For instance, many implementations may not allow loads, stores, branches or jumps within an ASMACRO defi nition. Refer to the Users Guide for each processor which implements this capability for a list of macros define and implemented by that processor, and for any specific restrictions imposed by that processo .

Encoding:

Format:

BEQZ rx, offset

Purpose:

Branch on Equal to Zero (Extended)

To test a GPR then do a PC-relative conditional branch.

Description:

if (GPR[rx] = 0) then branch

The 16-bit offset is shifted left 1 bit, sign-extended, and then added to the address of the instruction after the branch to form the target address. If the contents of GPR rx are equal to zero, the program branches to the target address.

Restrictions:

None

Operation:

I:    tgt_offset = sign_extend(offset || 0)
      condition = (GPR[Xlat(rx)] = 0GPRLEN)
      if condition then
         PC = PC + 4 + tgt_offset
      endif

Exceptions:

None

Programming Notes:

In MIPS16e mode, the branch offset is interpreted as halfword-aligned. This is unlike 32-bit MIPS mode, which interprets the offset value as word-aligned.

Encoding:

Format:

BNEZ rx, offset

Purpose:

Branch on Not Equal to Zero (Extended)

To test a GPR then do a PC-relative conditional branch.

Description:

if (GPR[rx] != 0) then branch

The 16-bit offset is shifted left 1 bit, sign-extended, and then added to the address of the instruction after the branch to form the target address. If the contents of GPR rx are not equal to zero, the program branches to the target address.

Restrictions:

None

Operation:

I:    tgt_offset = sign_extend(offset || 0)
      condition = (GPR[Xlat(rx)] != 0GPRLEN)
      if condition then
          PC = PC + 4 + tgt_offset
      endif

Exceptions:

None

Programming Notes:

In MIPS16e mode, the branch offset is interpreted as halfword-aligned. This is unlike 32-bit MIPS mode, which interprets the offset value as word-aligned.

Encoding:

Format:

B offset

Purpose:

Unconditional Branch (Extended)

To do an unconditional PC-relative branch.

Description:

branch

The 16-bit offset is shifted left 1 bit, sign-extended, and then added to the address of the instruction after the branch to form the target address. The program branches to the target address unconditionally.

Restrictions:

None

Operation:

I:    PC = PC + 4 + sign_extend(offset || 0)

Exceptions:

None

Programming Notes:

In MIPS16e mode, the branch offset is interpreted as halfword-aligned. This is unlike 32-bit MIPS mode, which interprets the offset value as word-aligned.

Encoding:

Format:

BREAK immediate

Purpose:

Breakpoint

To cause a Breakpoint exception.

Description:

A breakpoint exception occurs, immediately and unconditionally transferring control to the exception handler.

Restrictions:

None

Operation:

SignalException(Breakpoint)

Exceptions:

Breakpoint

Programming Notes:

The code fielis available for use as software parameters, butis retrieved by the exception handler only by loading the contents of the memory halfword containing the instruction.

Encoding:

Format:

BTEQZ offset

Purpose:

Branch on T Equal to Zero (Extended)

To test special register T then do a PC-relative conditional branch.

Description:

if (T = 0) then branch

The 16-bit offset is shifted left 1 bit, sign-extended, and then added to the address of the instruction after the branch to form the target address. If the contents of GPR 24 are equal to zero, the program branches to the target address.

Restrictions:

None

Operation:

I:    tgt_offset = sign_extend(offset || 0)
      condition = (GPR[24] = 0GPRLEN)
      if condition then
         PC = PC + 4 + tgt_offset
      endif

Exceptions:

None

Programming Notes:

In MIPS16e mode, the branch offset is interpreted as halfword-aligned. This is unlike 32-bit MIPS mode, which interprets the offset value as word-aligned.

Encoding:

Format:

BTNEZ offset

Purpose:

Branch on T Not Equal to Zero (Extended)

To test special register T then do a PC-relative conditional branch.

Description:

if (T != 0) then branch

The 16-bit offset is shifted left 1 bit, sign-extended, and then added to the address of the instruction after the branch to form the target address. If the contents of GPR 24 are not equal to zero, the program branches to the target address.

Restrictions:

None

Operation:

I:    tgt_offset = sign_extend(offset || 0)
      condition = (GPR[24] != 0GPRLEN)
      if condition then
         PC = PC + 4 + tgt_offset
      endif

Exceptions:

None

Programming Notes:

In MIPS16e mode, the branch offset is interpreted as halfword-aligned. This is unlike 32-bit MIPS mode, which interprets the offset value as word-aligned.

Encoding:

Format:

CMPI rx, immediate

Purpose:

Compare Immediate (Extended)

To compare a constant with the contents of a GPR.

Description:

 T = GPR[rx] XOR immediate

The 16-bitimmediate is zero-extended and Exclusive-ORed with the contents of GPR rx. The resultis placed into

GPR 24.

Restrictions:

None

Operation:

GPR[24] = GPR[Xlat(rx)] xor zero_extend(immediate)

Exceptions:

None

Encoding:

Format:

CMP rx, ry

Purpose:

Compare

To compare the contents of two GPRs.

Description:

T = GPR[rx] XOR GPR[ry]

The contents of GPR ry are Exclusive-ORed with the contents of GPR rx. The result is placed into GPR 24.

Restrictions:

None

Operation:

GPR[24] = GPR[Xlat(ry)] xor GPR[Xlat(rx)]

Exceptions:

None

Encoding:

Format:

DIV rx, ry

Purpose:

Divide Word

To divide 32-bit signed integers.

Description:

 (LO, HI) = GPR[rx] / GPR[ry]

The 32-bit word value in GPR rx is divided by the 32-bit value in GPR ry,treating both operands as signed values.

The 32-bit quotient is placed into special register LO, and the 32-bit remainder is placed into special register HI.

No arithmetic exception occurs under any circumstances.

Restrictions:

If the divisor in GPR ry is zero, the arithmetic result is UNPREDICTABLE.

Operation:

q = GPR[Xlat(rx)] div GPR[Xlat(ry)]
r = GPR[Xlat(rx)] mod GPR[Xlat(ry)]
LO = q
HI = r

Exceptions:

None

Programming Notes:

No arithmetic exception occurs under any circumstances. If divide-by-zero or overfl w conditions are detected and some action taken, then the divide instruction is typically followed by additional instructions to check for a zero divisor and/or for overfl w.

Ifthe divide is asynchronous then the zero-divisor check can execute in parallel with the divide. The action taken on either divide-by-zero or overfl w is either a convention within the program itself, or more typically within the system software; one possibility is to take a BREAK exception with a code fiel value to signal the problem to the system software.

As an example,the C programming language in a UNIX® environment expects division by zero to either terminate the program or execute a program-specifie signal handler. C does not expect overfl w to cause any exceptional condition. If the C compiler uses a divide instruction, it also emits code to test for a zero divisor and execute a BREAK instruction to inform the operating system if a zero is detected.

Where the size of the operands are known, software should place the shorter operand in GPR ry. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

In some processors the integer divide operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the divide so that other instructions can execute in parallel.

Historical Perspective:

In MIPS 1 through MIPS III, if either of the two instructions preceding the divide is an MFHI or MFLO, the result of the MFHI or MFLO is UNPREDICTABLE. Reads of the HI or LO special register must be separated from subsequent instructions that write to them by two or more instructions. This restriction was removed in MIPS IV and

MIPS32 and all subsequent levels of the architecture.

Encoding:

Format:

DIVU rx, ry

Purpose:

Divide Unsigned Word

To divide 32-bit unsigned integers.

Description:

 (LO, HI) = GPR[rx] / GPR[ry]

The 32-bit word value in GPR rx is divided by the 32-bit value in GPR ry, treating both operands as unsigned values.

The 32-bit quotient is placed into special register LO, and the 32-bit remainder is placed into special register HI.

Restrictions:

If the divisor in GPR ry is zero, the arithmetic result is UNPREDICTABLE.

Operation:

q = (0 || GPR[Xlat(rx)]) div (0 || GPR[Xlat(ry)])
r = (0 || GPR[Xlat(rx)]) mod (0 || GPR[Xlat(ry)])
LO = q
HI = r

Exceptions:

None

Programming Notes:

See "Programming Notes" for the DIV instruction.

Historical Perspective:

In MIPS 1 through MIPS III, if either of the two instructions preceding the divide is an MFHI or MFLO, the result of the MFHI or MFLO is UNPREDICTABLE. Reads of the HI or LO special register must be separated from subsequent instructions that write to them by two or more instructions. This restriction was removed in MIPS IV and

MIPS32 and all subsequent levels of the architecture.

Encoding:

Format:

JALRC ra, rx

Purpose:

To execute a procedure call to an instruction address in a register

Description:

 GPR[ra] = return_addr, PC = GPR[rx]

The program unconditionally jumps to the address contained in GPR rx, with no delay slotinstruction. The instruction sets the ISA Mode bit to the value in GPR rx bit 0.

The address of the instruction following the jump is placed into GPR 31. The value stored in GPR 31 bit 0 reflectthe current value of the ISA Mode bit.

Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.

The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.

Restrictions:

The effective target address in GPR rx must be naturally-aligned. If bit 0 is zero and bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.

Operation:

I:    GPR[31] = (PC + 2)GPRLEN-1..1 || ISAMode
      PC = GPR[Xlat(rx)]GPRLEN-1..1 || 0
      ISAMode = GPR[Xlat(rx)]0

Exceptions:

None.

Programming Notes:

Unlike most "jump" instructions in the MIPS instruction set, JALRC does not have a delay slot.

Encoding:

Format:

JALR ra, rx

Purpose:

To execute a procedure call to an instruction address in a register.

Description:

 GPR[ra] = return_addr, PC = GPR[rx]

The program unconditionally jumps to the address contained in GPR rx, with a delay of one instruction. The instruction sets the ISA Mode bit to the value in GPR rx bit 0.

The address ofthe instruction following the delay slotis placed into GPR 31. The value stored in GPR 31 bit 0 reflects the current alue of the ISA Mode bit.

Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.

The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.

Restrictions:

The effective target address in GPR rx must be naturally-aligned. If bit 0 is zero and bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.

An extended instruction should not be placed in a jump delay slot, because this causes one-half of an instruction to be executed.

Processor operation is UNPREDICTABLE if a branch or jump instruction is placed in the delay slot of a jump.

Operation:

I:    GPR[31] = (PC + 4)GPRLEN-1..1 || ISAMode
I+1:  PC = GPR[Xlat(rx)]GPRLEN-1..1 || 0
      ISAMode = GPR[Xlat(rx)]0

Exceptions:

None

Encoding:

Format:

JAL target

Purpose:

To execute a procedure call within the current 256 MB-aligned region and preserve the current ISA.

Description:

Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call. The value stored in GPR 31 bit 0 reflect the current value of the ISA Mode bit.

This is a PC-region branch (not PC-relative);the effective target address is in the "current" 256 MB-aligned region.

The low 28 bits of the target address is the target fielshifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).

Jump to the effective target address, preserving the ISA Mode bit. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself.

The opcode fieldescribes a generaljump-and-link operation, with the x fielas a variable. The individualinstructions, JAL and JALX have specific alues for this variables.

Restrictions:

An extended instruction should not be placed in a jump delay slot as it causes one-half of an instruction to be executed.

Processor operation is UNPREDICTABLE if a branch or jump instruction is placed in the delay slot of a jump.

Operation:

I:    GPR[31] = (PC + 6)GPRLEN-1..1 || ISAMode
I+1:  PC = PCGPRLEN-1..28 || target || 02

Exceptions:

None

Programming Notes:

Forming the jump target address by catenating PC and the 26-bittarget address rather than adding a signed offsetto the PC is an advantage if all program code addresses fi into a 256 MB region aligned on a 256 MB boundary.

It allows a branch from anywhere in the region to anywhere in the region, an action not allowed by a signed relative offset.

This definitiocreates the boundary case where the jump instruction is in the last word of a 256 MB region and can therefore jump only to the following 256 MB region containing the jump delay slot.

Encoding:

Format:

JALX target

Purpose:

To execute a procedure call within the current 256 MB-aligned region and change the ISA Mode from 32-bit MIPS to

MIPS16e.

Description:

Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call. The value stored in GPR 31 bit 0 reflect the current value of the ISA Mode bit.

This is a PC-region branch (not PC-relative);the effective target address is in the "current" 256 MB-aligned region.

The low 28 bits of the target address is the instr_index fielshifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).

Jump to the effective target address,toggling the ISA Mode bit. Execute the instruction that follows the jump,in the branch delay slot, before executing the jump itself.

Restrictions:

Processor operation is UNPREDICTABLE if a branch,jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.

Operation:

I:    GPR[31] = PC + 8
I+1:  PC = PCGPRLEN..28 || instr_index || 02
      ISAMode = (not ISAMode)

Exceptions:

None

Programming Notes:

Forming the branch target address by catenating PC and index bits rather than adding a signed offset to the PC is an advantage if all program code addresses fi into a 256 MB region aligned on a 256 MB boundary. It allows a branch from anywhere in the region to anywhere in the region, an action not allowed by a signed relative offset.

This definitiocreates the following boundary case: When the branch instruction is in the last word of a 256 MB region, it can branch only to the following 256 MB region containing the branch delay slot.

Encoding:

Format:

JRC ra

Purpose:

To execute a branch to the instruction address in the return address register.

Description:

PC = GPR[ra]

The program unconditionally jumps to the address specifiein GPR 31, with no delay slot instruction. The instruction sets the ISA Mode bit to the value in GPR 31 bit 0.

Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.

The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.

Restrictions:

The effective target address in GPR 31 must be naturally-aligned. If bit 0 is zero and bit 1 is one,then an Address

Error exception occurs when the jump target is subsequently fetched as an instruction.

Operation:

I: PC = GPR[31]GPRLEN-1..1 || 0
   ISAMode = GPR[31]0

Exceptions:

None.

Programming Notes:

Unlike most MIPS "jump" instructions, JRC does not have a delay slot.

Encoding:

Format:

JRC rx

Purpose:

To execute a branch to an instruction address in a register

Description:

PC = GPR[rx]

The program unconditionally jumps to the address specifiein GPR rx, with no delay slot instruction. The instruction sets the ISA Mode bit to the value in GPR rx bit 0.

Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.

The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.

Restrictions:

The effective target address in GPR rx must be naturally-aligned. If bit 0 is zero and bit 1 is one,then an Address

Error exception occurs when the jump target is subsequently fetched as an instruction.

Operation:

I: PC = GPR[Xlat(rx)]GPRLEN-1..1 || 0
   ISAMode = GPR[Xlat(rx)]0

Exceptions:

None.

Programming Notes:

Unlike most MIPS "jump" instructions, JRC does not have a delay slot.

Encoding:

Format:

JR ra

Purpose:

To execute a branch to the instruction address in the return address register.

Description:

 PC = GPR[ra]

The program unconditionally jumps to the address specifiein GPR 31, with a delay of one instruction. The instruction sets the ISA Mode bit to the value in GPR 31 bit 0.

Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.

The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.

Restrictions:

The effective target address in GPR 31 must be naturally-aligned. If bit 0 is zero and bit 1 is one,then an Address

Error exception occurs when the jump target is subsequently fetched as an instruction.

An extended instruction should not be placed in a jump delay slot, because this causes one-half of an instruction to be executed.

Processor operation is UNPREDICTABLE if a branch or jump instruction is placed in the delay slot of a jump.

Operation:

I+1:  PC = GPR[31]GPRLEN-1..1 || 0
      ISAMode = GPR[31]0

Exceptions:

None

Encoding:

Format:

JR rx

Purpose:

To execute a branch to an instruction address in a register.

Description:

PC = GPR[rx]

The program unconditionally jumps to the address specifiein GPR rx, with a delay of one instruction. The instruction sets the ISA Mode bit to the value in GPR rx bit 0.

Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.

The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.

Restrictions:

The effective target address in GPR rx must be naturally aligned. If bit 0 is zero and bit 1 is one,then an Address

Error exception occurs when the jump target is subsequently fetched as an instruction.

An extended instruction should not be placed in a jump delay slot, because this causes one-half of an instruction to be executed.

Processor operation is UNPREDICTABLE if a branch or jump instruction is placed in the delay slot of a jump.

Operation:

I+1:  PC = GPR[Xlat(rx)]GPRLEN-1..1 || 0
      ISAMode = GPR[Xlat(rx)]0

Exceptions:

None

Encoding:

Format:

LB ry, offset(rx)

Purpose:

Load Byte (Extended)

To load a byte from memory as a signed value.

Description:

GPR[ry] = memory[GPR[rx] + offset]

The 16-bit offset is sign-extended, then added to the contents of GPR rx to form the effective address. The contents of the byte at the memory location specified by the e fective address are sign-extended and loaded into GPR ry.

Restrictions:

None

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2)
memword = LoadMemory (CCA, BYTE, pAddr, vAddr, DATA)
byte = vAddr1..0 xor BigEndianCPU2
GPR[Xlat(ry)] = sign_extend(memword7+8*byte..8*byte)

Exceptions:

TLB Refill, TLB I valid, Bus Error, Address Error

Encoding:

Format:

LBU ry, offset(rx)

Purpose:

Load Byte Unsigned (Extended)

To load a byte from memory as an unsigned value

Description:

GPR[ry] = memory[GPR[rx] + offset]

The 16-bit offset is sign-extended, then added to the contents of GPR rx to form the effective address. The contents of the byte at the memory location specified by the e fective address are zero-extended and loaded into GPR ry.

Restrictions:

None

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2)
memword = LoadMemory (CCA, BYTE, pAddr, vAddr, DATA)
byte = vAddr1..0 xor BigEndianCPU2
GPR[Xlat(ry)] = zero_extend(memword7+8*byte..8*byte)

Exceptions:

TLB Refill, TLB I valid, Bus Error, Address Error

Encoding:

Format:

LH ry, offset(rx)

Purpose:

Load Halfword (Extended)

To load a halfword from memory as a signed value.

Description:

GPR[ry] = memory[GPR[rx] + offset]

The 16-bit offsetis sign-extended and then added to the contents of GPR rx to form the effective address. The contents of the halfword at the memory location specifie by the effective address are sign-extended and loaded into GPR

ry.

Restrictions:

The effective address must be naturally-aligned.Ifthe least-significanbit ofthe address is non-zero, an Address

Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
if vAddr0 != 0 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0 xor (ReverseEndian || 0))
memword = LoadMemory (CCA, HALFWORD, pAddr, vAddr, DATA)
byte = vAddr1..0 xor (BigEndianCPU || 0)
GPR[Xlat(ry)] = sign_extend(memword15+8*byte..8*byte)

Exceptions:

TLB Refill, TLB I valid, Bus Error, Address Error

Encoding:

Format:

LHU ry, offset(rx)

Purpose:

Load Halfword Unsigned (Extended)

To load a halfword from memory as an unsigned value.

Description:

GPR[ry] = memory[GPR[rx] + offset]

The 16-bit offsetis sign-extended and then added to the contents of GPR rx to form the effective address. The contents of the halfword at the memory location specifie by the effective address are zero-extended and loaded into GPR

ry.

Restrictions:

The effective address must be naturally-aligned.Ifthe least-significanbit ofthe address is non-zero, an Address

Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
if vAddr0 != 0 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0 xor (ReverseEndian || 0))
memword = LoadMemory (CCA, HALFWORD, pAddr, vAddr, DATA)
byte = vAddr1..0 xor (BigEndianCPU || 0)
GPR[Xlat(ry)] = zero_extend(memword15+8*byte..8*byte)

Exceptions:

TLB Refill, TLB I valid, Bus Error, Address Error

Encoding:

Format:

LI rx, immediate

Purpose:

Load Immediate (Extended)

To load a constant into a GPR.

Description:

GPR[rx] = immediate

The 16-bit immediate is zero-extended and then loaded into GPR rx.

Restrictions:

None

Operation:

GPR[Xlat(rx)] = zero_extend(immediate)

Exceptions:

None

Encoding:

Format:

LW rx, offset(pc)

Purpose:

Load Word (PC-Relative, Extended)

To load a PC-relative word from memory as a signed value.

Description:

GPR[rx] = memory[PC + offset]

The 16-bit offsetis sign-extended and added to the address of the LW instruction;this forms the effective address.

Before the addition,the 2 lower bits ofthe instruction address are cleared. The contents ofthe 32-bit word atthe memory location specified by the e fective address are loaded into GPR rx.

Restrictions:

A PC-relative, extended LW may not be placed in the delay slot of a jump instruction.

The effective address must be naturally-aligned. If either of the 2 least-significanbits of the address is non-zero, an

Address Error exception occurs.

Operation:

vAddr = (PCGPRLEN-1..2 || 02) + sign_extend(offset)
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
GPR[Xlat(rx)] = memword

Exceptions:

TLB Refill, TLB I valid, Bus Error, Address Error

Programming Note

For the purposes of watchpoints (provided by the CP0 WatchHi and WatchLo registers) and EJTAG breakpoints, the

PC-relative reference is considered to be a data, rather than an instruction reference. That is, the watchpoint or breakpoint is triggered only if enabled for data references.

Encoding:

Format:

LW rx, offset(sp)

Purpose:

Load Word (SP-Relative, Extended)

To load an SP-relative word from memory as a signed value.

Description:

GPR[rx] = memory[GPR[sp] + offset]

The 16-bit offsetis sign-extended and then added to the contents of GPR 29 to form the effective address. The contents of the word at the memory location specified by the e fective address are loaded into GPR rx.

Restrictions:

The effective address must be naturally-aligned. If either of the 2 least-significanbits of the address is non-zero, an

Address Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[29]
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
GPR[Xlat(ry)] = memword

Exceptions:

TLB Refill, TLB I valid, Bus Error, Address Error

Encoding:

Format:

LW ry, offset(rx)

Purpose:

Load Word (Extended)

To load a word from memory as a signed value.

Description:

GPR[ry] = memory[GPR[rx] + offset]

The 16-bit offsetis sign-extended and then added to the contents of GPR rx to form the effective address. The contents of the word at the memory location specified by the e fective address are loaded into GPR ry.

Restrictions:

The effective address must be naturally-aligned. If either of the 2 least-significanbits of the address is non-zero, an

Address Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
GPR[Xlat(ry)] = memword

Exceptions:

TLB Refill, TLB I valid, Bus Error, Address Error

Encoding:

Format:

MFHI rx

Purpose:

Move From HI Register

To copy the special purpose HI register to a GPR.

Description:

GPR[rx] = HI

The contents of special register HI are loaded into GPR rx.

Restrictions:

None

Operation:

GPR[Xlat(rx)] = HI

Exceptions:

None

Historical Information:

In the MIPS I, II, and III architectures, the two instructions which follow the MFHI must not moodify the HI register.

If this restriction is violated,the result of the MFHI is UNPREDICTABLE. This restriction was removed in MIPS

IV and MIPS32, and all subsequent levels of the architecture.

Encoding:

Format:

MFLO rx

Purpose:

Move From LO Register

To copy the special purpose LO register to a GPR.

Description:

GPR[rx] = LO

The contents of special register LO are loaded into GPR rx.

Restrictions:

None

Operation:

GPR[Xlat(rx)] = LO

Exceptions:

None

Historical Information:

In the MIPS I, II, and III architectures, the two instructions which follow the MFHI must not moodify the HI register.

If this restriction is violated,the result of the MFHI is UNPREDICTABLE. This restriction was removed in MIPS

IV and MIPS32, and all subsequent levels of the architecture.

Encoding:

Format:

MOVE r32, rz

Purpose:

Move

To move the contents of a GPR to a GPR.

Description:

GPR[r32] = GPR[rz]

The contents of GPR rz are moved into GPR r32, and r32 can specify any one of the 32 GPRs.

Restrictions:

None

Operation:

GPR[r32] = GPR[Xlat(rz)]

Exceptions:

None

Programming Notes:

The instruction word of 0x6500 (move $0,$16), expressed as NOP, is the assembly idiom used to

denote no operation.

Encoding:

Format:

MOVE ry, r32

Purpose:

Move

To move the contents of a GPR to a GPR.

Description:

GPR[ry] = GPR[r32]

The contents of GPR r32 are moved into GPR ry, and r32 can specify any one of the 32 GPRs.

Restrictions:

None

Operation:

GPR[Xlat(rz)] = GPR[r32]

Exceptions:

None

Encoding:

Format:

MULT rx, ry

Purpose:

Multiply Word

To multiply 32-bit signed integers.

Description:

(LO, HI) = GPR[rx] * GPR[ry]

The 32-bit word value in GPR rx is multiplied by the 32-bit value in GPR ry, treating both operands as signed values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the highorder 32-bit word is placed into special register HI.

No arithmetic exception occurs under any circumstances.

Restrictions:

None

Operation:

prod = GPR[Xlat(rx)] * GPR[Xlat(ry)]
LO = sign_extend(prod31..0)
HI = sign_extend(prod63..32)

Exceptions:

None

Programming Notes:

In some processors the integer multiply operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.

Programs that require overfl w detection must check for it explicitly.

Where the size of the operands are known, software should place the shorter operand in GPR rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

Encoding:

Format:

MULTU rx, ry

Purpose:

Multiply Unsigned Word

To multiply 32-bit unsigned integers.

Description:

(LO, HI) = GPR[rx] * GPR[ry]

The 32-bit word value in GPR rx is multiplied by the 32-bit value in GPR ry, treating both operands as unsigned values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the highorder 32-bit word is placed into special register HI.

No arithmetic exception occurs under any circumstances.

Restrictions:

None

Operation:

prod = (0 || GPR[Xlat(rx)]) * (0 || GPR[Xlat(ry)])
LO = sign_extend(prod31..0)
HI = sign_extend(prod63..32)

Exceptions:

None

Programming Notes:

In some processors the integer multiply operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.

Programs that require overfl w detection must check for it explicitly.

Where the size of the operands are known, software should place the shorter operand in GPR rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

Encoding:

Format:

NEG rx, ry

Purpose:

Negate

To negate an integer value.

Description:

GPR[rx] = 0 - GPR[ry]

The contents of GPR ry are subtracted from zero to form a 32-bit result. The result is placed in GPR rx.

Restrictions:

None

Operation:

temp = 0 - GPR[Xlat(ry)]
GPR[Xlat(rx)] = sign_extend(temp31..0)

Exceptions:

None

Encoding:

Format:

NOP

Purpose:

No Operation

To perform no operation.

Description:

NOP is the assembly idiom used to denote no operation. The actualinstruction is interpreted by the hardware as

MOVE $0,$16.

Restrictions:

None

Operation:

None

Exceptions:

None

Programming Notes:

The 0x6500 instruction word, which represents MOVE $0,$16, is the preferred NOP for software to use to filjump delay slots and to pad out alignment sequences.

Encoding:

Format:

NOT rx, ry

Purpose:

Not

To complement an integer value

Description:

GPR[rx] = (NOT GPR[ry])

The contents of GPR ry are bitwise-inverted and placed in GPR rx.

Restrictions:

None

Operation:

GPR[Xlat(rx)] = (not GPR[Xlat(ry)])

Exceptions:

None

Encoding:

Format:

OR rx, ry

Purpose:

Or

To do a bitwise logical OR.

Description:

GPR[rx] = GPR[rx] OR GPR[ry]

The contents of GPR ry are combined with the contents of GPR rx in a bitwise logical OR operation. The resultis placed in GPR rx.

Restrictions:

None

Operation:

GPR[Xlat(rx)] = GPR[Xlat(rx)] or GPR[Xlat(ry)]

Exceptions:

None

Encoding:

Format:

RESTORE {ra,}{s0/s1/s0-1,}{framesize} (All args are optional)

Purpose:

Restore Registers and Deallocate Stack Frame

To deallocate a stack frame before exit from a subroutine, restoring return address and static registers, and adjusting stack

Description:

GPR[ra] = Stack and/or GPR[17]= Stack and/or GPR[16]= Stack,sp = sp + (framesize*8)
sp = sp + (framesize*8)

Restore the ra and/or GPR 16 and/or GPR 17 (s0 and s1 in the MIPS ABI calling convention) registers from the stack if the corresponding ra, s0, ors1 bits of the instruction are set, and adjust the stack pointer by 8 times the framesize value. Registers are loaded from the stack assuming higher numbered registers are stored at higher stack addresses. A framesize value of 0 is interpreted as a stack adjustment of 128.

The opcode and function fieldescribe a general save/restore operation, with the s fieldas a variables. The individual instructions, RESTORE and SAVE have specific alues for this variable.

Restrictions:

If either of the 2 least-significan bits of the stack pointer are not zero, and any of the ra, s0, ors1 bits are set, then an

Address Error exception will occur.

Operation:

if framesize = 0 then
   temp = GPR[29] + 128
else
   temp = GPR[29] + (0 || (framesize << 3))
endif
temp2 = temp
if ra = 1 then
   temp = temp − 4
   GPR[31] = LoadStackWord(temp)
endif
if s1 = 1 then
   temp = temp - 4
   GPR[17] = LoadStackWord(temp)
endif
if s0 = 1 then
   temp = temp − 4
   GPR[16] = LoadStackWord(temp)
endif
GPR[29] = temp2
LoadStackWord(vaddr)
   if vAddr1..0 != 02 then
      SignalException(AddressError)
   endif
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
   memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
   LoadStackWord = memword
enfunction LoadStackWord

Exceptions:

TLB refill, TLB i valid, Address error, Bus Error

Programming Notes:

This instruction executes for a variable number of cycles and performs a variable number of loads from memory. A full restart of the sequence of operations will be performed on return from any exception taken during execution.

Encoding:

Format:

RESTORE {ra,}{xsregs,}{aregs,}{framesize}(All arguments optional)

Purpose:

Restore Registers and Deallocate Stack Frame (Extended)

To deallocate a stack frame before exitfrom a subroutine,restoring return address and static registersfrom an extended static register set, and adjusting the stack

Description:

GPR[ra] = Stack and/or GPR[18-23,30] =  Stack and/or GPR[17] =  Stackand/or GPR[16] = Stack and/or GPR[4-7] = Stack, sp = sp + (framesize * 8)

Restore the ra register from the stack if the ra bit is set in the instruction. Restore from the stack the number of registers in the set GPR[18-23,30] indicated by the value of the xsregs field Restore from the stack GPR 16 and/or GPR

17 (s0 and s1 in the MIPS ABI calling convention) from the stack if the corresponding s0 and s1 bits of the instruction are set, restore from the stack the number of registers in the range GPR[4-7] indicated by the aregs field

and adjust the stack pointer by 8 times the 8-bit concatenated framesize value. Registers are loaded from the stack assuming higher numbered registers are stored at higher stack addresses.

Interpretation of the aregs Field

In the standard MIPS ABIs, GPR[4-7] are designated as argument passing registers, a0-a3. When they are so used, they must be saved on the stack at locations allocated by the caller of the routine being entered, but need not be restored on subroutine exit.

In other MIPS16e calling sequences, however,itis possible that some ofthe registers

GPR[4-7] need to be saved as static registers on the local stack instead of on the caller stack, and restored before return from the subroutine. The encoding used for the aregs fiel of an extended RESTORE instruction is the same as that used for the extended SAVE, but since argument registers can be ignored for the purposes of a RESTORE, only the registers treated as static need be handled. The following table shows the RESTORE encoding of the aregs field

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Restrictions:

If either of the 2 least-significanbits of the stack pointer are not zero, and any of the ra, s0, s1, orxsregsfieldare non-zero or the aregs fiel contains an encoding that implies a register load, then an Address Error exception will occur.

Operation:

temp = GPR[29] + (0 || (framesize << 3))
temp2 = temp
if ra = 1 then
   temp = temp - 4
   GPR[31] = LoadStackWord(temp)
endif
if xsregs > 0 then
   if xsregs > 1 then
      if xsregs > 2 then
         if xsregs > 3 then
             if xsregs > 4 then
                if xsregs > 5 then
                   if xsregs> 6 then
                       temp = temp - 4
                       GPR[30] = LoadStackWord(temp)
                   endif
                   temp = temp - 4
                   GPR[23] = LoadStackWord(temp)
                endif
                temp = temp - 4
                GPR[22] = LoadStackWord(temp)
             endif
             temp = temp - 4
             GPR[21] = LoadStackWord(temp)
         endif
         temp = temp - 4
         GPR[20] = LoadStackWord(temp)
      endif
      temp = temp - 4
      GPR[19] = LoadStackWord(temp)
   endif
   temp = temp - 4
   GPR[18] = LoadStackWord(temp)
endif
if s1 = 1 then
   temp = temp - 4
   GPR[17] = LoadStackWord(temp)
endif
if s0 = 1 then
   temp = temp - 4
   GPR[16] = LoadStackWord(temp)
endif
case aregs of
   0b0000 0b0100 0b1000 0b1100 0b1110: astatic = 0
   0b0001 0b0101 0b1001 0b1101: astatic = 1
   0b0010 0b0110 0b1010: astatic = 2
   0b0011 0b0111: astatic = 3
   0b1011: astatic = 4
   otherwise: UNPREDICTABLE
endcase
if astatic > 0 then
   temp = temp - 4
   GPR[7] = LoadStackWord(temp)
   if astatic > 1 then
      temp = temp - 4
      GPR[6] = LoadStackWord(temp)
      if astatic > 2 then
          temp = temp - 4
          GPR[5] = LoadStackWord(temp)
          if astatic > 3 then
             temp = temp - 4
             GPR[4] = LoadStackWord(temp)
          endif
      endif
   endif
endif
GPR[29] = temp2
LoadStackWord(vaddr)
   if vAddr1..0 != 02 then
      SignalException(AddressError)
   endif
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
   memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
   LoadStackWord = memword
enfunction LoadStackWord

Exceptions:

TLB refill, TLB i valid, Address error, Bus Error

Programming Notes:

This instruction executes for a variable number of cycles and performs a variable number of loads from memory. A full restart of the sequence of operations will be performed on return from any exception taken during execution.

Behavior of the processor is UNPREDICTABLE for Reserved values of aregs.

Encoding:

Format:

SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)

Purpose:

Save Registers and Set Up Stack Frame

To set up a stack frame on entry to a subroutine, saving return address and static registers, and adjusting stack

Description:

Stack  = GPR[ra] and/or Stack = GPR[17] and/or Stack = GPR[16],sp = sp - (framesize * 8)

Save the ra and/or GPR 16 and/or GPR 17 (s0 and s1 in the MIPS ABI calling convention) on the stack if the corresponding ra, s0, and s1 bits of the instruction are set, and adjust the stack pointer by 8 times the framesize value. Registers are stored with higher numbered registers at higher stack addresses. A framesize value of 0 is interpreted as a stack adjustment of 128.

The opcode and function fieldescribe a general save/restore operation, with the s fieldas a variables. The individual instructions, RESTORE and SAVE have specific alues for this variable.

Restrictions:

If either of the 2 least-significan bits of the stack pointer are not zero, and any of the ra, s0, ors1bits are set, then an

Address Error exception will occur.

Operation:

temp = GPR[29]
if ra = 1 then
   temp = temp - 4
   StoreStackWord(temp, GPR[31])
endif
if s1 = 1 then
   temp = temp - 4
   StoreStackWord(temp, GPR[17])
endif
if s0 = 1 then
   temp = temp - 4
   StoreStackWord(temp, GPR[16])
endif
if framesize = 0 then
   temp = GPR[29] - 128
else
   temp = GPR[29] - (0 || (framesize << 3))
endif
GPR[29] = temp
StoreStackWord(vaddr, value)
   if vAddr1..0 != 02 then
      SignalException(AddressError)
   endif
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
   dataword = value
   StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA)
endfunction StoreStackWord

Exceptions:

TLB refill, TLB i valid, TLB modified, Address erro , Bus Error

Programming Notes:

This instruction executes for a variable number of cycles and performs a variable number of stores to memory. A full restart of the sequence of operations will be performed on return from any exception taken during execution.

Encoding:

Format:

SAVE {ra,}{xsregs,}{aregs,}{framesize} (All arguments optional)

Purpose:

Save Registers and Set Up Stack Frame (Extended)

To set up a stack frame on entry to a subroutine, saving return address, static, and argument registers, and adjusting the stack

Description:

Stack = GPR[ra] and/or Stack = GPR[18-23,30] and/or Stack = GPR[17] and/orStack = GPR[16] and/or Stack = GPR[4-7], sp = sp - (framesize * 8)

Save registers GPR[4-7] specifieto be treated as incoming arguments by the aregs field Save the ra register on the stack if the ra bit of the instruction is set. Save the number of registers in the set GPR[18-23, 30] indicated by the value of the xsregs field and/or GPR 16 and/or GPR 17 (s0 and s1 in the MIPS ABI calling convention) on the stack if the corresponding s0 and s1 bits of the instruction are set. Save the number of registers in the range GPR[4-7] that are to be treated as static registers as indicated by the aregs field and adjust the stack pointer by 8 times the 8-bit concatenated framesize value. Registers are stored with higher numbered registers at higher stack addresses.

Interpretation of the aregs Field

In the standard MIPS ABIs, GPR[4-7] are designated as argument passing registers, a0-a3. When they are so used, they must be saved on the stack at locations allocated by the caller of the routine being entered. In other MIPS16e calling sequences, however, it is possible that some of the registers GPR[4-7] will need to be saved as static registers on the local stack instead of on the caller stack. The encoding of the aregs fiel allows for 0-4 arguments, 0-4 statics, and for mixtures of the two. Registers are bound to arguments in ascending order, a0, a1, a2, and a3, and thus assigned to static values in the reverse order, GPR[7], GPR[6], GPR[5], and GPR[4]. The following table shows the encoding of the aregs field

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Restrictions:

If either of the 2 least-significanbits of the stack pointer are not zero, and any of the ra, s0, s1, orxsregsfieldare non-zero or the aregs field contains an alue that implies a register store, then an Address Error exception will occur.

Operation:

temp = GPR[29]
temp2 = GPR[29]
case aregs of
   0b0000 0b0001 0b0010 0b0011 0b1011: args = 0
   0b0100 0b0101 0b0110 0b0111: args = 1
   0b1000 0b1001 0b1010: args = 2
   0b1100 0b1101: args = 3
   0b1110: args = 4
   otherwise: UNPREDICTABLE
endcase
if args > 0 then
   StoreStackWord(temp, GPR[4])
   if args > 1 then
      StoreStackWord(temp + 4, GPR[5])
      if args > 2 then
         StoreStackWord(temp + 8, GPR[6])
         if args > 3 then
             StoreStackWord(temp + 12, GPR[7])
         endif
      endif
   endif
endif
if ra = 1 then
   temp = temp - 4
   StoreStackWord(temp, GPR[31])
endif
if xsregs > 0 then
   if xsregs > 1 then
      if xsregs > 2 then
         if xsregs > 3 then
             if xsregs > 4 then
                if xsregs > 5 then
                   if xsregs > 6 then
                       temp = temp - 4
                       StoreStackWord(temp, GPR[30])
                   endif
                   temp = temp - 4
                   StoreStackWord(temp, GPR[23])
                endif
                temp = temp - 4
                StoreStackWord(temp, GPR[22])
             endif
             temp = temp - 4
             StoreStackWord(temp, GPR[21])
         endif
         temp = temp - 4
         StoreStackWord(temp, GPR[20])
      endif
      temp = temp - 4
      StoreStackWord(temp, GPR[19])
   endif
   temp = temp - 4
   StoreStackWord(temp, GPR[18])
endif
if s1 = 1 then
   temp = temp - 4
   StoreStackWord(temp, GPR[17])
endif
if s0 = 1 then
   temp = temp - 4
   StoreStackWord(temp, GPR[16])
endif
case aregs of
   0b0000 0b0100 0b1000 0b1100 0b1110: astatic = 0
   0b0001 0b0101 0b1001 0b1101: astatic = 1
   0b0010 0b0110 0b1010: astatic = 2
   0b0011 0b0111: astatic = 3
   0b1011: astatic = 4
   otherwise: UNPREDICTABLE
endcase
if astatic > 0 then
   temp = temp - 4
   StoreStackWord(temp, GPR[7])
   if astatic > 1 then
      temp = temp - 4
      StoreStackWord(temp, GPR[6])
      if astatic > 2 then
         temp = temp - 4
         StoreStackWord(temp, GPR[5])
         if astatic > 3 then
             temp = temp - 4
             StoreStackWord(temp, GPR[4])
         endif
      endif
   endif
endif
temp = temp2 - (0 || (framesize << 3))
GPR[29] = temp
StoreStackWord(vaddr, value)
   if vAddr1..0 != 02 then
      SignalException(AddressError)
   endif
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
   dataword = value
   StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA)
endfunction StoreStackWord

Exceptions:

TLB refill, TLB i valid, TLB modified, Address erro , Bus Error

Programming Notes:

This instruction executes for a variable number of cycles and performs a variable number of stores to memory. A full restart of the sequence of operations will be performed on return from any exception taken during execution.

Behavior of the processor is UNPREDICTABLE for Reserved values of aregs.

Encoding:

Format:

SB ry, offset(rx)

Purpose:

Store Byte (Extended)

To store a byte to memory.

Description:

memory[GPR[rx] + offset] = GPR[ry]

The 16-bit offsetis sign-extended and then added to the contents of GPR rx to form the effective address. The leastsignificant byte of GP

ry is stored at the effective address.

Restrictions:

None

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2)
bytesel = vAddr1..0 xor BigEndianCPU2
dataword = GPR[rt]31-8*bytesel..0 || 08*bytesel
StoreMemory (CCA, BYTE, dataword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB I valid, TLB Modified, Bus Erro , Address Error

Encoding:

Format:

SDBBP code

Purpose:

Software Debug Breakpoint

To cause a debug breakpoint exception

Description:

This instruction causes a debug exception, passing control to the debug exception handler. If the processor is executing in Debug Mode when the SDBBP instruction is executed the exception is a Debug Mode Exception, which sets the DebugDExcCode fiel to the value 0x9 (Bp). The code fiel can be used for passing information to the debug exception handler, and is retrieved by the debug exception handler only by loading the contents of the memory word containing the instruction, using the DEPC register. The CODE field is not used in a y way by the hardware.

Restrictions:

Operation:

If DebugDM = 0 then
   SignalDebugBreakpointException()
else
   SignalDebugModeBreakpointException()
endif

Exceptions:

Debug Breakpoint Exception

Debug Mode Breakpoint Exception

Encoding:

Format:

SEB rx

Purpose:

Sign-Extend Byte

Sign-extend least significant byte in r gister rx.

Description:

GPR[rx] = sign_extend(GPR[rx]7..0)

The least significant byte of GPrx is sign-extended and the value written back to rx.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)]
GPR[Xlat(rx)] = sign_extend(temp7..0)

Exceptions:

None.

Programming Notes:

None.

Encoding:

Format:

SEH rx

Purpose:

Sign-Extend Halfword

Sign-extend least significantord in register rx.

Description:

GPR[rx] = sign_extend(GPR[rx]15..0);

The least significant halford of GPR rx is sign-extended and the value written back to rx.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)]
GPR[Xlat(rx)] = sign_extend(temp15..0)

Exceptions:

None.

Programming Notes:

None.

Encoding:

Format:

SH ry, offset(rx)

Purpose:

Store Halfword (Extended)

To store a halfword to memory.

Description:

memory[GPR[rx] + offset] = GPR[ry]

The 16-bit offsetis sign-extended and then added to the contents of GPR rx to form the effective address. The leastsignificant half ord of GPR ry is stored at the effective address.

Restrictions:

The effective address must be naturally-aligned.Ifthe least-significanbit ofthe address is non-zero, an Address

Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
if vAddr0 != 0 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..2 || (pAddr11..0 xor (ReverseEndian || 0))
bytesel = vAddr11..0 xor (BigEndianCPU || 0)
dataword = GPR[Xlat(ry)]31-8*bytesel..0|| 08*bytesel
StoreMemory (CCA, HALFWORD, dataword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB I valid, TLB Modified, Bus Erro , Address Error

Encoding:

Format:

SLL rx, ry, sa

Purpose:

Shift Word Left Logical (Extended)

To execute a left-shift of a word by a fi ed number of bits-0 to 31 bits.

Description:

GPR[rx] = GPR[ry] << sa

The 32-bit contents of GPR ry are shifted left, and zeros are inserted into the emptied low-order bits. The 5-bit sa field specifies the shift amount. The result is placed into G

rx.

Restrictions:

None

Operation:

s = sa
temp = GPR[Xlat(ry)](31-s)..0|| 0s
GPR[Xlat(rx)] = temp

Exceptions:

None

Encoding:

Format:

SLLV ry, rx

Purpose:

Shift Word Left Logical Variable

To execute a left-shift of a word by a variable number of bits.

Description:

GPR[ry] = GPR[ry] << GPR[rx]

The 32-bit contents of GPR ry are shifted left, and zeros are inserted into the emptied low-order bits; the result word is and placed back in GPR ry. The 5 low-order bits of GPR rx specify the shift amount.

Restrictions:

None

Operation:

s = GPR[Xlat(rx)]4..0
temp = GPR[Xlat(ry)](31-s)..0|| 0s
GPR[Xlat(ry)] = temp

Exceptions:

None

Encoding:

Format:

SLTI rx, immediate

Purpose:

Set on Less Than Immediate (Extended)

To record the result of a less-than comparison with a constant.

Description:

T = (GPR[rx] < immediate)

The 16-bitimmediate is sign-extended and subtracted from the contents of GPR rx. Considering both quantities as signed integers, if GPR rx is less than the sign-extended immediate, the result is set to 1 (true); otherwise, the result is set to 0 (false). The result is placed into GPR 24.

Restrictions:

None

Operation:

if GPR[Xlat(rx)] < sign_extend(immediate) then
   GPR[24] = 0GPRLEN-1 || 1
else
   GPR[24] = 0GPRLEN
endif

Exceptions:

None

Encoding:

Format:

SLTIU rx, immediate

Purpose:

Set on Less Than Immediate Unsigned (Extended)

To record the result of an unsigned less-than comparison with a constant.

Description:

T = (GPR[rx] < immediate)

The 16-bitimmediate is sign-extended and subtracted from the contents of GPR rx. Considering both quantities as unsigned integers, if GPR rx is less than the sign-extended immediate, the result is set to 1 (true); otherwise, the result is set to 0 (false). The result is placed into GPR 24.

Restrictions:

None

Operation:

if (0 || GPR[Xlat(rx)]) < (0 || sign_extend(immediate)) then
   GPR[24] = 0GPRLEN-1 || 1
else
   GPR[24] = 0GPRLEN
endif

Exceptions:

None

Encoding:

Format:

SLT rx, ry

Purpose:

Set on Less Than

To record the result of a less-than comparison.

Description:

T = (GPR[rx] < GPR[ry])

The contents of GPR ry are subtracted from the contents of GPR rx. Considering both quantities as signed integers, if the contents of GPR rx are less than the contents of GPR ry, the result is set to 1 (true); otherwise, the result is set to 0

(false). This result is placed into GPR 24.

Restrictions:

None

Operation:

if GPR[Xlat(rx)] < GPR[Xlat(ry)] then
   GPR[24] = 0GPRLEN-1 || 1
else
   GPR[24] = 0GPRLEN
endif

Exceptions:

None

Encoding:

Format:

SLTU rx, ry

Purpose:

Set on Less Than Unsigned

To record the result of an unsigned less-than comparison.

Description:

T = (GPR[rx] < GPR[ry])

The contents of GPR ry are subtracted from the contents of GPR rx. Considering both quantities as unsigned integers, if the contents of GPR rx are less than the contents of GPR ry, set the result to 1 (true); otherwise, set the result to 0

(false). The result is placed into GPR 24.

Restrictions:

None

Operation:

if (0 || GPR[Xlat(rx)]) < (0 || GPR[Xlat(ry)]) then
   GPR[24] = 0GPRLEN-1 || 1
else
   GPR[24] = 0GPRLEN
endif

Exceptions:

None

Encoding:

Format:

SRA rx, ry, sa

Purpose:

Shift Word Right Arithmetic (Extended)

To execute an arithmetic right-shift of a word by a fi ed number of bits-0 to 31bits.

Description:

GPR[rx] = GPR[ry] >> sa (arithmetic)

The 32-bit contents of GPR ry are shifted right, and the sign bit is replicated into the emptied high-order bits. The 5bit sa field specifies the shift amount. The result is placed into G

rx.

Restrictions:

None

Operation:

s = sa
temp = (GPR[Xlat(ry)]31)s || GPR[Xlat(ry)]31..s
GPR[Xlat(rx)] = sign_extend(temp31..0)

Exceptions:

None

Encoding:

Format:

SRAV ry, rx

Purpose:

Shift Word Right Arithmetic Variable

To execute an arithmetic right-shift of a word by a variable number of bits.

Description:

GPR[ry] = GPR[ry] >> GPR[rx] (arithmetic)

The 32-bit contents of GPR ry are shifted right, and the sign bitis replicated into the emptied high-order bits;the word result is placed back in GPR ry. The 5 low-order bits of GPR rx specify the shift amount.

Restrictions:

None

Operation:

s = GPR[Xlat(rx)]4..0
temp = (GPR[Xlat(ry)]31)s || GPR[Xlat(ry)]31..s
GPR[Xlat(ry)] = temp

Exceptions:

None

Encoding:

Format:

SRL rx, ry, sa

Purpose:

Shift Word Right Logical (Extended)

To execute a logical right-shift of a word by a fi ed number of bits-0 to 31 bits.

Description:

GPR[rx] = GPR[ry] >> sa (logical)

The 32-bit contents of GPR ry are shifted right, and zeros are inserted into the emptied high-order bits. The 5-bit sa field specifies the shift amount. The result is placed into G

rx.

Restrictions:

None

Operation:

s = sa
temp = 0s || GPR[Xlat(ry)]31..s
GPR[Xlat(rx)] = temp

Exceptions:

None

Encoding:

Format:

SRLV ry, rx

Purpose:

Shift Word Right Logical Variable

To execute a logical right-shift of a word by a variable number of bits.

Description:

GPR[ry] = GPR[ry] >> GPR[rx] (logical)

The 32-bit contents of GPR ry are shifted right, and zeros are inserted into the emptied high-order bits;the word result is placed back in GPR ry. The 5 low-order bits of GPR rx specify the shift amount.

Restrictions:

None

Operation:

s = GPR[Xlat(rx)]4..0
temp = 0s || GPR[Xlat(ry)]31..s
GPR[Xlat(ry)] = temp

Exceptions:

None

Encoding:

Format:

SUBU rz, rx, ry

Purpose:

Subtract Unsigned Word

To subtract 32-bit integers.

Description:

GPR[rz] = GPR[rx] - GPR[ry]

The 32-bit word value in GPR ry is subtracted from the 32-bit value in GPR rx and the 32-bit arithmetic resultis placed into GPR rz.

No integer overfl w exception occurs under any circumstances.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)] - GPR[Xlat(ry)]
GPR[Xlat(rz)] = (temp)

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer;this operation is 32-bit modulo arithmetic that does not trap on overfl w. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overfl w, such as C language arithmetic.

Encoding:

Format:

SW ra, offset(sp)

Purpose:

Store Word

ra

(SP-Relative, Extended)

To store register ra SP-relative to memory.

Description:

memory[sp + offset] = ra

The 16-bit offsetis sign-extended and then added to the contents of GPR 29 to form the effective address. The contents of GPR 31 are stored at the effective address.

Restrictions:

The effective address must be naturally-aligned. If either of the 2 least-significanbits of the address is non-zero, an

Address Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[29]
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
dataword = GPR[31]
StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB I valid, TLB Modified, Address Erro

Encoding:

Format:

SW rx, offset(sp)

Purpose:

Store Word

rx

(SP-Relative, Extended)

To store an SP-relative word to memory.

Description:

memory[GPR[sp] + offset] = GPR[rx]

The 16-bit offsetis sign-extended and then added to the contents of GPR 29 to form the effective address. The contents of GPR rx are stored at the effective address.

Restrictions:

The effective address must be naturally-aligned. If either of the two least-significan bits of the address is non-zero, an

Address Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[29]
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
dataword = GPR[Xlat(rx)]
StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB I valid, TLB Modified, Bus Erro , Address Error

Encoding:

Format:

SW ry, offset(rx)

Purpose:

Store Word (Extended)

To store a word to memory.

Description:

memory[GPR[rx] + offset] = GPR[ry]

The 16-bit offsetis sign-extended and then added to the contents of GPR rx to form the effective address. The contents of GPR ry are stored at the effective address.

Restrictions:

The effective address must be naturally-aligned. If either of the 2 least-significanbits of the address is non-zero, an

Address Error exception occurs.

Operation:

vAddr = sign_extend(offset) + GPR[Xlat(rx)]
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
dataword = GPR[Xlat(ry)]
StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB I valid, TLB Modified, Bus Erro , Address Error

Encoding:

Format:

XOR rx, ry

Purpose:

Exclusive OR

To do a bitwise logical Exclusive OR.

Description:

GPR[rx] = GPR[rx] XOR GPR[ry]

The contents of GPR ry are combined with the contents of GPR rx in a bitwise Exclusive OR operation. The result is placed in GPR rx.

Restrictions:

None

Operation:

GPR[Xlat(rx)] = GPR[Xlat(rx)] xor GPR[Xlat(ry)]

Exceptions:

None

Encoding:

Format:

ZEB rx

Purpose:

Zero-Extend Byte

Zero-extend least significant byte in r gister rx.

Description:

GPR[rx] = zero_extend(GPR[rx]7..0);

The least significant byte of GPrx is zero-extended and the value written back to rx.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)]
GPR[Xlat(rx)] = 0 || temp7..0

Exceptions:

None

Programming Notes:

None

Encoding:

Format:

ZEH rx

Purpose:

Zero-Extend Halfword

Zero-extend least significant halford in register rx.

Description:

GPR[rx] = zero_extend(GPR[rx]15..0);

The least significant halford of GPR rx is zero-extended and the value written back to rx.

Restrictions:

None

Operation:

temp = GPR[Xlat(rx)]
GPR[Xlat(rx)] = 0 || temp15..0

Exceptions:

None

Programming Notes:

None