Encoding:

Format:

SWL rx, immediate(rb)

Purpose:

Store Word Left Extended

To store the most-significant part of a word to an unaligned memory address.

Description:

 memory[GPR[rb] + immediate] = GPR[rx]

The 9-bit signed immediate value is added to the contents of GPR rb to form an effective address (EffAddr). EffAddr is the address of the most-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.

A part of W (the most-significant 1 to 4 bytes) is in the aligned word containing EffAddr. The same number of the most-significant (left) bytes from the word in GPR rx are stored into these bytes of W.

The following figure illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The four consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W (2 bytes) is located in the aligned word containing the most-significant byte at 2.

3.SWL stores the most-significant 2 bytes of the low word from the source register into these 2 bytes in memory.

4.The complementary SWR stores the remainder of the unaligned word.

The bytes stored from the source register to memory depend on both the offset of the effective address within an aligned word-that is, the low 2 bits of the address (vAddr1..0)-and the current byte-ordering mode of the processor

(big- or little-endian). The following figure shows the bytes stored for every combination of offset and byte ordering.

Restrictions:

Unpredictable prior to MIPS16e2.

Operation:

vAddr = sign_extend(immediate) + GPR[Xlat[rb]]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0  xor  ReverseEndian2)
If BigEndianMem = 0 then
   pAddr = pAddrPSIZE-1..2 || 02
endif
byte = vAddr1..0 xor BigEndianCPU2
dataword = 024-8*byte || GPR[Xlat[rx]]31..24-8*byte
StoreMemory(CCA, byte, dataword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Bus Error, Address Error, Watch