Encoding:

EXTEND

11110

Imm[8:5]

SWSP

11010

sel = 6

Imm[4:0]

Format:

SC rx, immediate(rb)

MIPS16e2

Store Conditional Word Extended

Purpose:

Store Conditional Word Extended

To store a word to memory to complete an atomic read-modify-write.

Description:

 if atomic_update then memory[GPR[rb] + immediate] = GPR[rx], GPR[rx] = 1 else GPR[rx] = 0

The LL and SC instructions provide primitives to implement atomic read-modify-write (RMW) operations on synchronizable memory locations.

The 32-bit word in GPR rx is conditionally stored in memory at the location specified by the aligned effective address. The signed immediate value is added to the contents of GPR rb to form an effective address.

The SC completes the RMW sequence begun by the preceding LL instruction executed on the processor. To complete the RMW sequence atomically, the following occur:

The 32-bit word of GPR rx is stored to memory at the location specified by the aligned effective address.
A one, indicating success, is written into GPR rx.

Otherwise, memory is not modified and a 0, indicating failure, is written into GPR rx

If the following event occurs between the execution of LL and SC, the SC fails:

A coherent store is executed between an LL and SC sequence on the same processor to the block of synchronizable physical memory containing the word (if Config5LLB=1; else whether such a store causes the SC to fail is not predictable).

An ERET instruction is executed.

Furthermore, an SC must always compare its address against that of the LL. An SC will fail if the aligned address of the SC does not match that of the preceeding LL.

A load that executes on the processor executing the LL/SC sequence to the block of synchronizable physical memory containing the word, will not cause the SC to fail (if Config5LLB=1; else such a load may cause the SC to fail).

If any of the events listed below occurs between the execution of LL and SC, the SC may fail where it could have succeeded, i.e., success is not predictable. Portable programs should not cause any of these events.

A load or store executed on the processor executing the LL and SC that is not to the block of synchronizable physical memory containing the word. (The load or store may cause a cache eviction between the LL and SC that results in SC failure. The load or store does not necessarily have to occur between the LL and SC.)

Any prefetch that is executed on the processor executing the LL and SC sequence (due to a cache eviction between the LL and SC).

A non-coherent store executed between an LL and SC sequence to the block of synchronizable physical memory containing the word.

The instructions executed starting with the LL and ending with the SC do not lie in a 2048-byte contiguous region of virtual memory. (The region does not have to be aligned, other than the alignment required for instruction words.)

CACHE operations that are local to the processor executing the LL/SC sequence will result in unpredictable behaviour of the SC if executed between the LL and SC, that is, they may cause the SC to fail where it could have succeeded. Non-local CACHE operations (address-type with coherent CCA) may cause an SC to fail on either the local processor or on the remote processor in multiprocessor or multi-threaded systems. This definition of the effects of

CACHE operations is mandated if Config5_LLB=1. If Config5_LLB=0, then CACHE effects are implementation-dependent.

The following conditions must be true or the result of the SC is not predictable-the SC may fail or succeed (if

Config5_LLB=1, then either success or failure is mandated, else the result is UNPREDICTABLE):

Execution of SC must have been preceded by execution of an LL instruction.
An RMW sequence executed without intervening events that would cause the SC to fail must use the same address in the LL and SC. The address is the same if the virtual address, physical address, and cacheability & coherency attribute are identical.

Restrictions:

Unpredictable prior to MIPS16e2. The effective address must be naturally-aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs.

Operation:

vAddr = sign_extend(immediate) + GPR[Xlat[rb]]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
dataword= GPR[Xlat[rx]]
if LLbit then
   StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA)
endif
GPR[Xlat[rx]] = 0³¹|| LLbit
LLbit = 0 // if Config5_LLB=1, SC always clears LLbit regardless of address match.

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch

Programming Notes:

LL and SC are used to atomically update memory locations, as shown below.

L1:
   LL    a1, (a0)  # load counter
   ADDIU v0, a1, 1 # increment
   SC    v0, (a0)  # try to store, checking for atomicity
   BEQ   v0, 0, L1 # if not atomic (0), try again
   NOP             # branch-delay slot

Exceptions between the LL and SC cause SC to fail, so persistent exceptions must be avoided. Some examples of these are arithmetic operations that trap, system calls, and floating point operations that trap or require software emulation assistance.

LL and SC function on a single processor for cached noncoherent memory so that parallel programs can be run on uniprocessor systems that do not support cached coherent memory access types.